A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

A portable self contained light generating device which is powered by a flow of granular material falling under the influence of gravity to impinge upon and cause a paddle wheel to rotate thereby turning a small generator producing electricity to power one or more light emitting diodes for illumination. The device equipped with a multi-position power/illumination control switch and in some embodiments also provided with a battery providing supplemental power.

A system and method for tracking and informing about a physical, emotional, or physiological cycle, such as a menstrual cycle, includes at least one definition entry and at least one date indicator. Each definition entry defines indicia such as color to represent a stage of a physical, emotional, or physiological cycle. Each date indicator includes a date section and a tracking section corresponding to each date section. The date section of the date indicator indicates at least one date, wherein the tracking section is capable of being marked so as to indicate indicia corresponding to a definition entry to signify the stage of the physical, emotional, or physiological cycle for each date. According to one embodiment, the date indicators are arranged according to phases of the moon to allow correlation of a user's cycle to the lunar cycle.

A musical rhythm is expressed by the number of the timing marks (for example, three timing marks when in simple triple time); and a musical tempo is expressed by the distance among the timing marks and a timing ball that moves at a fixed speed among those timing marks. Accordingly, a player may easily grasp the tempo of the music and easily determine the rhythm of the music in a sound game.

A method for detecting and conveying an alarm signal, when an absorbent article is unfastened or, completely removed from the body of the wearer. The method is intended to be used in parallel with a method for detecting wetness in the absorbent article and further relates to an integrated detection-and-alarm method for detecting unfastening and/or wetness in an absorbent article. A system for detecting and conveying an alarm signal when an absorbent article is unfastened or removed from the body of the wearer and/or when the article is wet. The system includes (a) and absorbent article having at least one absorbent layer, the object to be displaced, such as a fastening system, one or more sensoring devices, one or more transmitting devices, and (b) a remote receiver. Furthermore, the system relates to the use of the system in the care of children and adults suffering from incontinence and/or psychological illnesses.

The coupled resonator comprises a first low frequency resonator, such as a balance spring (1) and a second higher frequency resonator, such as a tuning fork (2), the two resonators (1 and 2) including permanent mechanical coupling means. Application to the regulating system of a timepiece.

A tunable resonator is provided that has a high Q for each resonate frequency. The tunable resonator is a MEMs tunable resonator wherein the tuner is affected by moving a moveable mass, associated with the resonating portion of the resonator, form a first position to a second position such that the moveable mass is held in the first position or second position by a detent rather than a constant electromagnet magnetic or electrostatic force applied thereon.

Smoking cessation lighter is configured for lighting cigarettes for a smoker, and learning software is provided for monitoring smoking behavior of a smoker during a first data collection period and guiding a smoker's smoking cessation by directing the smoker when the smoker is to smoke a cigarette based on data collected during the first data collection period. The learning software monitors user behavior and collects data during use of the lighter by the smoker after the initial data collection period in order to analyze and further guide the smoker based on the smoker's cheating behavior, the smoker's behavior of lighting a cigarette for a friend, and the smoker's behavior of skipping use of the lighter at a time when the smoker has been directed to light a cigarette by the lighter.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

Various systems and methods are described for configuring a data storage system. In one embodiment, a plurality of actual capacities of a plurality of storage devices of the data storage system are identified and divided into a plurality of capacity slices. The plurality of capacity slices are combined into a plurality of chunks of capacity slices, each having a combination of characteristics of the underlying physical storage devices. The chunks of capacity slices are then mapped to a plurality of logical storage devices. A group of the plurality of logical storage devices is then organized into a redundant array of logical storage devices.

A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset. A class variable may be associated with storage devices of a stripeset to identify the type of data that the stripeset can store. The class variable may be increased (or otherwise modified) when a computer stores data of a different class in the stripeset.

Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

A computing system includes a plurality of dispersed storage (DS) processing units operable to receive a continuous data stream, simultaneously disperse storage error encode the continuous data stream to produce a plurality of encoded data slices and store the plurality of encoded data slices in a DS memory.

A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments.

For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations.

A flash memory file system including a plurality of flash modules. Each of the plurality of flash modules includes a respective cache memory, a respective flash memory, and a respective flash controller in communication with the respective cache memory and the respective flash memory. A first flash module of the plurality of flash modules is configured to receive a file lookup message including a path name for file data stored on a second flash module of the plurality of flash modules. A third flash module of the plurality of flash modules is configured to select the second flash module based on the path name and a directory table, and generate a file metadata message responsive to the file lookup message. The file metadata message identifies the second flash module as containing the file data.

Provided is a method and system for reducing duplicate buffers in buffer cache associated with a storage device. Reducing buffer duplication in a buffer cache includes accessing a file reference pointer associated with a file in a deduplicated filesystem when attempting to load a requested data block from the file into the buffer cache. To determine if the requested data block is already in the buffer cache, aspects of the invention compare a fingerprint that identifies the requested data block against one or more fingerprints identifying a corresponding one or more sharable data blocks in the buffer cache. A match between the fingerprint of the requested data block and the fingerprint from a sharable data block in the buffer cache indicates that the requested data block is already loaded in buffer cache. The sharable data block in buffer cache is used instead thereby reducing buffer duplication in the buffer cache.

A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a lower level cache that is also present in a higher level cache. Furthermore, the CBI utility selects the cache-line for eviction from an LRU group. The CBI utility ensures that dormant cache-lines in the higher level caches do not retain corresponding presence bits set in the lower level caches by unsetting the presence bits in the lower level cache when a line is replaced in the higher level cache. Additionally, when a processor core becomes idle, the CBI utility invalidates the corresponding higher level cache by unsetting the corresponding presence bits in the lower level cache.

Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit.

A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.

Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.

System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements. The source virtual machine file is converted by transforming the HM data elements of the source file to create destination HM data elements in a destination hypervisor format different from the source hypervisor format; maintaining the locations of the VMP data elements stored on the persistent storage media constant during the conversion from source to destination file formats without reading or writing the VMP data elements; and creating indirections to reference the destination HM data elements in the destination hypervisor format and the existing stored VMP data elements.

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.

A method and apparatus are disclosed of monitoring a number of virtual machines operating in an enterprise network. One example method of operation may include identifying a number of virtual machines currently operating in an enterprise network and determining performance metrics for each of the virtual machines. The method may also include identifying at least one candidate virtual machine from the virtual machines to optimize its active application load and modifying the candidate virtual machine to change its active application load.

Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.

In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.

The present invention provides α-keto alkylperacids and methods for producing and using the same. In particular, α-keto alkylperacids are useful as antimicrobial agents.

In a process for the separation and drying of crude carboxylic acid crystals from a slurry in a solvent, the slurry is supplied to a filter operating at pressure and at a temperature above the atmospheric boiling point of the solvent. A cake of separated crystals is removed from the filter and passed to a thermal dryer. In a system for the separation and drying of crude carboxylic acid from a slurry in a solvent, a pressure filter device has a slurry inlet and an outlet for a cake of carboxylic acid crystals. The system also has a thermal dryer and means for transporting the cake of carboxylic acid crystals from the pressure filter device to the dryer. The pressure filter device is configured to operate at a pressure and temperature above the atmospheric boiling point of the solvent.

A process is provided for recovering aliphatic monocarboxylic acids having from 4 to 11 carbon atoms from the distillation residue obtained in the oxidation of the corresponding aldehyde by means of oxygen or oxygen-containing gas mixtures in the presence of alkali metal carboxylates or alkaline earth metal carboxylates to form the corresponding monocarboxylic acid and subsequent distillation, characterized in that the distillation residue is reacted with an aqueous acid in a tube reactor and the two-phase mixture flowing out from the tube reactor is introduced into a settling vessel in which the organic phase which separates out has a pH of 4.5 or less.

The present invention relates to the use of at least one sulfonic acid for recovering glycerol resulting from a reaction crude from transesterification of glycerides, in particular of triglycerides of vegetable and/or animal origin. The invention also relates to a process for purifying glycerol obtained as a by-product of triglyceride transesterification during the preparation of fatty acids, fatty esters and/or fatty acid salts, and also to a combined process for preparing, on the one hand, fatty acids, fatty esters and/or fatty acid salts and, on the other hand, glycerol, from triglycerides, using at least one sulfonic acid.

A reaction system suitable for production of a methionine salt contains a reactive rectification column containing a weir having a height of 100 mm or more.

According to one embodiment, an actinic-ray- or radiation-sensitive resin composition includes any of the compounds (A) of general formula (I) below that when exposed to actinic rays or radiation, generates an acid and a resin (B) whose rate of dissolution into an alkali developer is increased by the action of an acid. (The characters used in general formula (I) have the meanings mentioned in the description.)

The invention features methods and compositions for the synthesis of multimerizing agents. An exemplary method for producing AP20187 may comprise: (a) coupling 2-N,Ndimethylaminomethyl-1,3-diaminopropane with AP20792 to produce the dimeric alcohol, AP20793; and (b) coupling the AP20793 so produced with API7362 to yield AP20187. In particular embodiments, the method further includes the step of producing API7362 by coupling API7360 with methyl-L-pipecolic acid, or a salt thereof.