A wearable device has a carrier having an aperture. A device has a USB connection and a protrusion wherein the protrusion is received in the aperture to connect the device to a wristband. The device is a USB type device having athletic functionality. The device may further be configured to receive calibration data such that a measured distance may be converted to a known distance based on athletic activity performed by a user.

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

Methods, devices and system are provided. One method includes capturing activity data associated with activity of a user via a device. The activity data is captured over time, and the activity data is quantifiable by a plurality of metrics. The method includes storing the activity data in storage of the device and, from time to time, connecting the device with a computing device over a wireless communication link. The method defines using a first transfer rate for transferring activity data captured and stored over a period of time. The first transfer rate is used following startup of an activity tracking application on the computing device The method also defines using a second transfer rate for transferring activity data from the device to the computing device for display of the activity data in substantial-real time on the computing device.

The present invention provides a shift register unit, a shift register circuit, an array substrate and a display device, and relates to the area of display manufacturing. The time of the bias working on the de-noising transistor can be reduced without affecting the circuit stability, so that the operational lifespan of the device can be extended. A shift register comprises: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a de-noising control model. The present invention is used for manufacturing displays.

A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

A reset circuit for Gate Driver on Array, an array substrate and a display is used for increasing reliability and long-term stability of a GOA circuit and thus improving performance of the GOA circuit. The GOA reset circuit includes a first electronic switch circuit (301) connected to an input terminal of a GOA unit of the Gate Driver on Array (INPUT); and a second electronic switch circuit connected to an output terminal of the GOA unit (OUTPUT), wherein the first electronic switch circuit (301) is connected to a low level signal terminal and is switched on to connect the low level signal terminal to a reset terminal of the GOA unit (RESET) when the input terminal of the GOA unit (INPUT) is at a high level; and the second electronic switch circuit (302) is connected to a high level signal terminal and is switched on to connect the high level signal terminal to the reset terminal of the GOA unit (RESET) when the output terminal of the GOA unit (OUTPUT) is at a high level.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

A stage constituent circuit of a display device drive circuit includes a first-node to a third-node, a thin-film transistor that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor that changes a potential of a different stage control signal toward a potential of a clock when a potential of the second-node is in the HIGH level, a capacitor between the first-node and the second-node, and a capacitor between the second-node and the third-node. The potential of the first-node is raised on the basis of a different stage control signal output from the stage constituent circuit in the different stage, and then the potential of the second-node and a potential of the third-node are sequentially raised. Herein, an amplitude of the clock is set to be smaller than an amplitude of the scanning signal.

Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.

A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A bilateral cargo strap system is provided as a means of securing a variety of different cargo within a storage area. The bilateral cargo strap system utilizes a combination of elastic straps with perpendicularly positioned stabilizing rods to improve retention of a variety of cargo within a storage area. The elastic straps extend over the retained cargo and are used as the means of engaging mounting features within the storage area. The stabilizing rods effectively distribute the tension force of the elastic straps over the retained cargo securing it in place within the storage space. The bilateral cargo strap system is versatile and may be used to secure a wide variety of cargo including, but not limited to, kayaks, coolers, bicycles, lumber, and construction equipment.

A low profile hold down assembly is mounted to the exterior surface of a sidewall of a trailer. The hold down assembly includes a cover member formed from the same material from which the sidewall of the trailer is formed and therefore is aesthetically desirable.

A vehicle restraint system includes a strap assembly configured to be positioned on a portion of a tire of a vehicle to secure the vehicle to a deck of a transport. The strap assembly is also configured to be coupled to the deck of the transport on a first side of the tire of the vehicle. The system also includes a mandrel assembly operable to be coupled to the strap assembly on a second side of the tire of the vehicle, opposite the first side. The system further includes a winch assembly configured to be coupled to the deck of the transport and the mandrel assembly on the second side of the tire of the vehicle, the winch assembly configured to rotate the mandrel assembly to produce a tightening force to tighten the strap assembly around the portion of the tire. The system still further includes a release mechanism disposed between the winch assembly and the mandrel assembly and configured to create a coupling between the winch assembly and the mandrel assembly in a manner that transmits the tightening force from the winch assembly to the mandrel assembly. The release mechanism is configured to release the coupling between the winch assembly and the mandrel assembly when a force greater than or equal to a predetermined force is produced against the release mechanism.

A transportation and storage system for a wind turbine rotor blade comprises a tip end frame assembly comprising a tip end receptacle and a tip end frame. The tip end receptacle comprises an upwardly open tip end-receiving space for receiving a portion of the tip end of the blade and having a supporting surface for supporting the blade, a lower surface allowing the tip end receptacle to rest upright on a substantially horizontal surface, such as the ground, and releasable retaining means for releasably retaining the tip end of the blade in the receiving space of the tip end receptacle. The tip end frame comprises an upwardly open receptacle-receiving space for receiving the receptacle and provided with positioning means for positioning the receptacle in the tip end frame. A base part defines a bottom surface allowing the tip end frame to rest upright on the ground.

A transport system for transporting large items wherein the large items comprise at least three through going holes and said system comprises a frame to support the items. Said frame has a substantially rectangular shape and comprises two parallel longitudinal beams connected by two parallel transverse beams and further comprises at least two transverse support bars to support the items, which transverse support bars are located between the two parallel transverse beams. The transport system further comprises a first and a second rod to be mounted in two through going holes in the items where each end of the first and second rod can be connected to the longitudinal beams to secure the items to the frame in such a way that no part of the large items extends over the rectangle defined by the two parallel longitudinal beams and the two parallel transverse beams.

Some embodiments include a novel laced strapping system that provides a plurality of attachment points by which a tie-down lace can adjust the fit of a cargo mesh webbing to secure loads of items in an open bed of a vehicle. In some embodiments, the vehicle is a pick-up truck with a cargo bed. In some embodiments, the mesh webbing comprises a first truck bed mesh, a second truck bed mesh, and the plurality of attachment points. In some embodiments, tie-down lace interconnects the attachment points to secure together the first mesh and the second mesh.

A rail mounting system includes a mounting rail that has a channel profile. The mounting rail is secured to a cargo area surface. Further, the rail mounting system includes a slide member that has a securement receiving area for securing a cargo product and the slide member within the channel profile of the mounting rail. The slide member is received within the channel profile.

A pallet system includes a pallet upon which cargo or other payloads may be carried. The pallet has a plurality of tie-down locations at which the pallet may be tied-down on a base, and at least one tie-down device for tying down the pallet on the base at any of the tie-down locations. The pallet further includes structure for mounting the tie-down device on the pallet at any of the tie-down locations.

An improved captive beam decking system is disclosed for use in a cargo trailer. The system includes a beam assembly and a foot assembly that is selectively engagable to a vertical sliding track system. The sliding track system is attached to the sidewall of a trailer vertically. The beam can be easily moved at different heights that are selected based upon the configuration of the cargo trailer.

An example wheel restraint includes a track to be positioned adjacent a vehicle approach path of a loading dock. A shuttle is pivotally coupled to the track via a track follower and pivots between a home position and a deployed position about a shuttle axis substantially parallel to and offset relative to a longitudinal axis of the track. A barrier is pivotally coupled to the shuttle and pivots between a non-blocking position and a blocking position about a pivot axis substantially parallel to and spaced apart from the longitudinal axis of the track such that the shuttle rotates in a first direction about the shuttle axis when the shuttle moves from the home position to the deployed position and bather rotates in a second direction about the pivot axis when the barrier moves from the non-blocking position to the blocking position, where the first direction being different than the second direction.

A transport system for a wind turbine blade is provided. The transport system is configured for increasing a curvature of the wind turbine blade in response to an obstacle during transport of the wind turbine blade. Further, a method for transporting a wind turbine blade in order to avoid obstacles is provided.

A module in the form of a pallet or a closed container includes a grouping together of the electrical devices in an avionics bay, in which the electrical devices are interconnected and attached so as to facilitate the mounting and thus limit the time it takes to mount the electrical devices in the avionics bay.

A fastening system includes an energy absorbing or impact indicator and at least one or more of the following: (1) a fastening base for mounting in an emergency vehicle, (2) a patient support engageable with a base, (3) a patient securement mechanism for securing a patient on a patient support, (4) a patient securement mechanism for securing a patient to a vehicle, (5) a patient support securement mechanism operable to secure a patient support in an emergency vehicle, or (6) a patient support securement mechanism operable to secure a patient support to a base, wherein the energy absorbing or impact indicator is located (1) at the patient securement mechanism, or (2) at the patient support securement mechanism, or wherein the energy absorbing or impact indicator is between (1) the base and the vehicle, (2) the patient support and the base, (3) the patient securement mechanism and the patient support, (4) the patient support and the emergency vehicle, (5) the patient and the emergency vehicle, or (6) the patient securement mechanism and the emergency vehicle, wherein the energy absorbing device or impact indicator has at least an energy absorbing state and a rigid state or indicates a level of impact at or between any of the respective component or components.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

The combination of: a) a storage unit associated with an over-the-road vehicle, the storage unit having an internal wall surface bounding a storage space and including spaced and facing first and second wall surfaces and a floor surface; and b) a cargo support system. The cargo support system has first and second vertically extending tracks operatively mounted on each to the first and second wall surface and at least a first elongate beam having spaced first and second ends attached respectively to the first and second tracks in an operative position spaced above the floor surface. At least one of the tracks is maintained operatively mounted to the first wall surface through the use of an adhesive.

Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.