According to a map display device, from current location information acquired by a current location acquiring unit 6 and boundary coordinate information in time zone information acquired by a time zone information acquiring unit 22, it is determined whether or not a vehicle 9 is located within a set area which is provided in the range of a predetermined distance from a boundary of a time zone to which a current location of the vehicle 9 belongs, and if it is determined that the vehicle 9 is located within the set area, a display unit 3 displays distinctively the time zone to which the current location of the vehicle 9 belongs and a time zone which is adjacent to the corresponding time zone through the set area.

Traffic information readings corresponding to a vehicle are received, the readings including at least a location. The traffic information readings are compared to information already within a map database, and are used to derive additional map information augmenting or correcting that already within the database, the additional map information subsequently being stored in the database. Additional information that is derived includes the presence of stop signs and traffic lights at intersections, the legality of turns at certain times of day, and the connectedness or non-connectedness of road segments.

A map display device includes: current location calculating unit for calculating a current location; specific region dedicated database for storing map data permitted only inside a specific region; specific region permitted database for storing data for displaying the inside of the specific region outside the specific region; outside-specific-region database for storing map data of the outside of the specific region available both inside and outside the specific region; controller for generating display data for displaying a map of the outside of the specific region using map data from the outside-specific-region database, and generating display data for displaying an image of a permitted map attribute to the inside of the specific region using the data from the permitted database, when the current location is outside the specific region; and display unit for displaying an image of the map or the permitted map attribute based on the display data.

A navigation system having a central device which uses a link shape compression unit to compress information of altitude changes of a road link obtained from a three-dimensional road map, and calculates a geometry parameter based on variation of energy of a vehicle travelling on the road link. An on-board terminal device estimates the vehicle's average travelling pattern by using a travel-pattern-estimation unit based on the geometry parameter calculated by the central device, a link-travelling time estimated from statistically-stored traffic information, and a link length. The on-board terminal device further calculates fuel consumption of the vehicle travelling on each road link based on the estimated travelling pattern and parameters of the vehicle by using a fuel-consumption calculation unit, and then, searches a fuel-efficient route by using the fuel consumption as a link cost. The on-board terminal device has a vehicle-type selector for selecting a type of the vehicle.

A navigation system may calculate a route to a destination and output guidance information with an output device to guide a user of the navigation system along the calculated route. If it is determined that a navigation device has left the calculated route, the navigation system may prompt the user asking whether output of guidance information should be suspended. If the output of guidance information should be suspended, the navigation system may suspend the output of guidance information and calculate a new route to the destination while the output of guidance information is suspended. The navigation system may calculate an estimated arrival time at the destination based on the calculated new route and output the estimated arrival time while the output of guidance information is suspended.

A method and apparatus for determining a trajectory for a vehicle are disclosed, wherein, the method includes: identifying a starting position (p0) and a desired terminal position (P) for the vehicle; linearly approximating dynamics of the vehicle; and using the starting position (p0), desired terminal position (P), and linear approximation, determining the trajectory for the vehicle. The linear approximation can be constrained by requirements (e.g., specifications) that: (i) an acceleration applied to the vehicle at a point on the trajectory is relatively large when the acceleration acts in a direction that is substantially perpendicular to the velocity of the vehicle; and (ii) an acceleration applied to the vehicle at a point on the trajectory is relatively small when the acceleration acts in a direction that is substantially parallel to the velocity of the vehicle. The vehicle may have a curvature limit.

An automated process uses a local positioning system to acquire location (i.e., position and orientation) data for one or more movable target objects. In cases where the target objects have the capability to move under computer control, this automated process can use the measured location data to control the position and orientation of such target objects. The system leverages the measurement and image capture capability of the local positioning system, and integrates controllable marker lights, image processing, and coordinate transformation computation to provide tracking information for vehicle location control. The resulting system enables position and orientation tracking of objects in a reference coordinate system.

A method of operation of a navigation system includes: receiving an origin and a destination; receiving a route keyword for routing between the origin and the destination; identifying a via point matching the route keyword; calculating a keyword group locale based on the via point within a group distance threshold from a keyword group center; and calculating a travel route from the origin to the destination traversing the keyword group locale for displaying on a device.

A navigation system and various methods of using the system are described herein. Search query results are refined by the system and are prioritized based at least in part upon sub-search categories selected during the searching process. Sub-searches can be represented by graphical icons displayed on the user interface.

The present invention relates to a control system and a method for a hybrid vehicle which may optimally control the operating point of a vehicle. A control method for a hybrid vehicle includes detecting driving requests and a state of charge (SOC) of a battery when the vehicle is driving in HEV mode, determining a motor operating point and an engine operating point when the battery is in low SOC state, and compensating the motor operating point and the engine operating point by applying a climbing degree of the vehicle and the atmospheric pressure.

A parking assist system includes: an actuator that drives a back door of a vehicle; an opening degree control unit that controls an opening degree of the back door by controlling the actuator; a storage device that stores an allowable opening degree of the back door at a park position of the vehicle in association with the park position; and a position information acquisition unit that acquires position information of the vehicle. When a position of the vehicle corresponds to the park position stored in the storage device, the opening degree control unit limits the opening degree of the back door on the basis of the allowable opening degree of the back door, stored in the storage device in association with the park position.

A method of monitoring an engine coolant system includes modeling the total energy stored within an engine coolant. If an actual temperature of the engine coolant is below a minimum target temperature, the modeled total energy stored within the energy coolant is compared to a maximum stored energy limit to determine if sufficient energy exists within the engine coolant to heat the engine coolant to a temperature equal to or greater than the minimum target temperature. The engine coolant system fails the diagnostic check when the modeled total energy stored within the energy coolant is greater than the maximum stored energy limit, and the minimum target temperature has not been reached.

A control device for a hybrid vehicle includes a portion determining whether an engine torque is necessary, a portion controlling a motor to make a motor torque be a target torque, an engine rotation speed control portion controlling an engine output shaft to rotate at a target engine rotation speed for sudden start/reacceleration while the clutch being disengaged after starting the engine and before an actual rotation speed of the engine output shaft exceeds a reference target engine rotation speed in a case where the engine torque is necessary, a control portion engaging the clutch after the actual rotation speed exceeds the reference target engine rotation speed, and a portion controlling the engine so that the engine torque is assumed to be a target torque by canceling the control by the engine rotation speed control portion after the actual rotation speed exceeds the reference target engine rotation speed.

Vehicle event recorder systems are arranged to be in constant communication with remote servers and administrators via mobile wireless cellular networks. Vehicle event recorders equipped with video cameras capture video and other data records of important events relating to vehicle use. These data are then transmitted over special communications networks having very high coverage space but limited bandwidth. A vehicle may be operated over very large region while maintaining continuous communications connections with a remote fixed server. As such, systems of these inventions may be characterized as including a mobile unit having: a video camera; a microprocessor; memory; an event trigger; and mobile wireless transceivers, and a fixed network portion including: mobile wireless cellular network, a protocol translation gateway, the Internet and an application-specific server.

A traction control system in vehicle comprises a detector for detecting a monitored value which changes according to a degree of a drive wheel slip; a condition determiner for determining whether or not the monitored value meets a control start condition and whether or not the monitored value meets a control termination condition; and a controller for executing traction control to reduce a driving power of the drive wheel during a period of time from when the condition determiner determines that the monitored value meets the control start condition until the condition determiner determines that the monitored value meets the control termination condition; the condition determiner being configured to set at least the control start condition variably based on a slip determination factor which changes according to a vehicle state and such that the control start condition changes more greatly according to the vehicle state than the control termination condition.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Methods for the design of microwave filters comprises comprising preferably the steps of inputting a first set of filter requirements, inputting a selection of circuit element types, inputting a selection of lossless circuit response variables, calculating normalized circuit element values based on the input parameters, and generate a first circuit, insert parasitic effects to the normalized circuit element values of the first circuit, and output at least the first circuit including the post-parasitic effect circuit values. Additional optional steps include: requirements to a normalized design space, performing an equivalent circuit transformation, unmapping the circuit to a real design space, performing a survey, and element removal optimization. Computer implement software, systems, and microwave filters designed in accordance with the method are included.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.

A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

A cleaning composition for sanitizing and/or disinfecting hard surfaces, comprising: a cationic biocide, surfactant and low levels of VOC solvents. The cleaning composition is adapted to clean a variety of hard surfaces without leaving behind a visible residue and creates low levels of streaking and filming on the treated surface. The cleaning composition contains less than 5% by weight of VOCs. The cleaning composition may be used alone as a liquid or spray formulation or in combination with a substrate, for example, a pre-loaded cleaning wipe.

A composition is described containing a branched nonionic surfactant of Formula (I): (I) wherein x is a real number from 1 to 11, y is a real number from 1 to 20, R 1 is an alkyl group having 1 to 3 carbon atoms, R 2 is an alkyl group having 4 to 6 carbon atoms, and a primary 5 alcohol ethoxylate.

The present invention provides personal care compositions comprising a carrier and a mixture of essential oil components having specific levels of eucalyptol, terpene materials and auxiliary fragrance materials. The compositions herein gentle to skin and have a fragrance and activity similar if the composition were made using the pure extracted essential oil.

The present invention is a solid rinse aid composition and methods of making and using the same. Applicants have surprisingly found that the crystal modifier sodium xylene sulfonate (short chain alkyl benzene or alkyl naphthalene sulfonates) at higher percentage can act as a solidification agent. The solid rinse aid composition generally includes an short chain alkyl benzene or alkyl naphthalene sulfonates solidification agent and an effective amount of a surfactant which can include a sheeting agent component, defoamer component and/or association disruption agent. The solid rinse aid composition may be phosphate-free, aminocarboxylate-free, and GRAS if desired.

The invention relates to compositions and methods of treatment employing compositions comprising polyelectrolyte complexes. The compositions include a water-soluble first polyelectrolyte bearing a net cationic charge or capable of developing a net cationic charge and a water-soluble second polyelectrolyte bearing a net anionic charge or capable of developing a net anionic charge. The total polyelectrolyte concentration of the first solution is at least 110 millimolar. The composition is free of coacervates, precipitates, latex particles, synthetic block copolymers, silicone copolymers, cross-linked poly(acrylic) and cross-linked water-soluble polyelectrolyte. The composition may be a concentrate, to be diluted prior to use to treat a surface.

A cleansing composition for cosmetic or household use may include an ampholytic polymer; a crosslinked cationic polymer; a surfactant component selected from the group consisting of anionic surfactants, amphoteric surfactants, cationic surfactants, nonionic surfactants, and zwitterionic surfactants; and an aqueous and/or organic carrier.

The invention relates to compositions including a hypohalite or hypochlorous acid and a soluble salt of 2,4,6 mesitylene sulfonate. The compositions may include a surfactant, a buffer, or combinations thereof. Other adjuvants may also be present. Such compositions do not require the inclusion of high concentrations of sodium hydroxide or other soluble hydroxide salts to drastically increase pH (and thus stability), although such hydroxides may be present if desired.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

A rinse-off composition, such as a shampoo, hair conditioner or shower gel, comprising a rinse-off composition base, lactoyl ethanolamine and at least one compound selected from the group consisting of N-(4-cyanomethylphenyl) p-menthanecarboxamide and N-(2-pyridin-2-ylethyl) p-menthanecarboxamide. The compositions provide a pleasant, long-lasting cooling sensation.

The use of ferric hydroxycarboxylate as a chelator and builder for cleaning compositions is disclosed. The cleaning composition may be formulated for warewashing, laundering, and for other means of removing soils and includes a ferric hydroxycarboxylate, an alkalinity source and a surfactant system. The cleaning composition has a pH of between about 9 and about 12.