A diphosphite is provided derived from phosphorous trihalide, tetra alkyl hindered bisphenol, and a neoalkyl diol. The phosphites exhibit improved stability and are useful as thermal oxidative stabilizers for thermoplastic compositions.

A diphosphite is provided derived from phosphorous trihalide, tetra alkyl hindered bisphenol, and a neoalkyl diol. The phosphites exhibit improved stability and are useful as thermal oxidative stabilizers for thermoplastic compositions.

A diphosphite is provided derived from phosphorous trihalide, tetra alkyl hindered bisphenol, and a neoalkyl diol. The phosphites exhibit improved stability and are useful as thermal oxidative stabilizers for thermoplastic compositions.

Provided is a light-emitting glass which is applicable to, e.g., white illuminators including a light-emitting diode as a light source, and which emits light of a warm white color when irradiated with near ultraviolet light and combines long-term weatherability with high heat resistance; a light-emitting device containing same and a process for producing same. The light-emitting glass includes, as the base glass, borosilicate or silicate glass having a separated-phase structure, whereby the base glass is efficiently doped with, for example, transition metal ion clusters which emit light of a warm white color upon irradiation with near ultraviolet light. With this glass, it is possible to attain increases in excitation wavelength and emission wavelength. The glass thus emits, based on a multiple scattering effect, high-intensity light of a warm white color upon irradiation with near ultraviolet light.

The instant invention provides for novel cationic lipids that can be used in combination with other lipid components such as cholesterol and PEG-lipids to form lipid nanoparticles with oligonucleotides. It is an object of the instant invention to provide a cationic lipid scaffold that demonstrates enhanced efficacy along with lower liver toxicity as a result of lower lipid levels in the liver. The present invention employs low molecular weight cationic lipids with one short lipid chain to enhance the efficiency and tolerability of in vivo delivery of siRNA.

A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.

Hydroswellable, absorbable and non-absorbable, aliphatic, segmented polyurethanes and polyurethane-urea capable of swelling in the biological environment with associated increase in volume of at least 3 percent have more than one type of segments, including those derived from polyethylene glycol and the molecular chains are structurally tailored to allow the use of corresponding formulations and medical devices as carriers for bioactive agents, rheological modifiers of cyanoacrylate-based tissue adhesives, as protective devices for repairing defective or diseased components of articulating joints and their cartilage, and scaffolds for cartilage tissue engineering.

A method for preparing poly(butylene terephthalate-co-adipate) copolymer by polymerizing 1,4-butane diol, an adipic acid component and an aromatic dicarboxy compound derived from polyethylene terephthalate, and a polyester component residue in the presence of a catalyst under conditions effective to form poly(butylene terephthalate-co-adipate) oligomers; adding a quencher; and reacting the quenched poly(butylene terephthalate-co-adipate) oligomers with a chain extender.

Amphiphilic biomimetic phosphorylcholine-containing silicone compounds for use in both topical and internal applications as components in biomedical devices. The silicone compounds, which include zwitterionic phosphorylcholine groups, may be polymerizable or non-polymerizable. Specific examples of applications include use as active functional components in ophthalmic lenses, ophthalmic lens care solutions, liquid bandages, wound dressings, and lubricious and anti-thrombogenic coatings.

The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an input of an accumulator stage (267) having an accumulator feedback output (269) selectively coupled to an input of the multiplier stage over a plurality of clock cycles; iteratively calculating a final working loop variable z over an additional plurality of clock cycles; multiplying the final working loop variable z and a complex input vector x to compute a final multiplier value; and adding a least significant complex polynomial coefficient to the final multiplier value using the multiplier stage of the multiply and accumulate feedback apparatus to yield a result of the polynomial evaluation.

Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

The various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). In one aspect, a portion of memory (e.g., a page in a block of a flash memory device) may be programmed many (e.g., 1000) times before an erase is required. Some embodiments include systems, methods and/or devices to integrate Bloom filter functionality in a non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to an unused location in the memory.

A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

A detection device for detecting the manner in which a peripheral device is removed from an electronic device is proposed. The detection device can be on the peripheral device or the electronic device and detects whether the peripheral device was removed in a manner that indicates the removal was intentional or unintentional.

A method for sharing peripheral devices in dual operating systems for an electronic device having at least one peripheral device is provided. The method includes: receiving a setting value for the peripheral device under the first operating system from a user; activating a second operating system; transmitting the setting value to the second operating system; and switching from the first operating system to the second operating system, wherein the second operating system sets the peripheral device with the setting value and enables the electronic device to operate under the second operating system.

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment.

It is to provide a technique for preventing aggregation or caking of menthol at the time of its keeping. In addition, it is to provide a lipid composition, which can show excellent thermal stability even in the case of high temperature at the time of keeping menthol and at the time of blending in a product, does not cause mutual aggregation of powders, particles, flakes, pellets, sticks and the like of menthol, and can maintain its shape retention property. From 10 to 50% by mass of sterols are added to and mixed with from 50 to 90% by mass of menthol, and the resultant is melted with heating. Paraffins may be further added and mixed in an amount of 20% by mass or less, based on the lipid composition.

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

Apparatus and methods are provided for using automatic speech recognition to analyze a voice interaction and verify compliance of an agent reading a script to a client during the voice interaction. In one aspect of the invention, a communications system includes a user interface, a communications network, and a call center having an automatic speech recognition component. In other aspects of the invention, a script compliance method includes the steps of conducting a voice interaction between an agent and a client and evaluating the voice interaction with an automatic speech recognition component adapted to analyze the voice interaction and determine whether the agent has adequately followed the script. In yet still further aspects of the invention, the duration of a given interaction can be analyzed, either apart from or in combination with the script compliance analysis above, to seek to identify instances of agent non-compliance, of fraud, or of quality-analysis issues.

A computerized method of presenting information from a variety of sources on a display device. Specifically the present invention describes a graphical user interface for organizing the simultaneous display of information from a multitude of information sources. In particular, the present invention comprises a graphical user interface which organizes content from a variety of information sources into a grid of tiles, each of which can refresh its content independently of the others. The grid functionality manages the refresh rates of the multiple information sources. The present invention is intended to operate in a platform independent manner.

A remote manipulation apparatus includes a main body and a manipulating handle manipulated by a user to move to cover all the orientations from a manipulation basis position defined on a basis of the main body. Movement of the manipulating handle relative to the manipulation basis position corresponds to movement of a pointer image relative to a screen basis position on a screen of a display apparatus. An auxiliary navigational display window includes a specified button image assigned with pointer-pulling information. When the auxiliary navigational display window appears on the screen, the manipulating handle is automatically driven to a position that corresponds to a position of the specified button image on the screen so that the pointer image is moved onto the specified button image that is assigned with the pointer-pulling information.

User interfaces for displaying relationships between cells in a grid. In one example embodiment, a user interface includes a grid including rows and columns and a plurality of cells each having a specific position in the grid. A first one of the cells is related to a second one of the cells. The grid is configured to display, upon selection of the first cell or second cell, a visual representation of the relationship between the first cell and the second cell.

A system for translating user motion into multiple object responses of an on-screen object based on user interaction of an application executing on a computing device is provided. User motion data is received from a capture device from one or more users. The user motion data corresponds to user interaction with an on-screen object presented in the application. The on-screen object corresponds to an object other than an on-screen representation of a user that is displayed by the computing device. The user motion data is automatically translated into multiple object responses of the on-screen object. The multiple object responses of the on-screen object are simultaneously displayed to the users.

Novel oxidized thiophospholipids are provided herein, as well as methods for producing same, and uses thereof in treating or preventing an inflammation associated with endogenous oxidized lipids and related conditions. Exemplary oxidized thiophospholipid according to embodiments described herein have the formula: wherein X1, X2, A1, A2, B', B″, D' and D″ are as described herein.

The present disclosure is directed to, in part, an aliphatic polycarbonate polymerization reaction initiated by combining an epoxide with carbon dioxide in the presence of a catalytic transition metal-ligand complex to form a reaction mixture, and further quenching that polymerization reaction by contacting the reaction mixture with an acid containing a non-nucleophilic anion produces a crude polymer solution with improved stability and processability.

In order to allow a single user registered on a single local host or other machine to access multiple shared resources on a remote host, an aliasing mechanism is employed so that multiple concurrent connections can be established by the user to a single remote host, with each connection using a different identity. Each connection can therefore be used to access a different shared resource on the remote host. In some illustrative examples, a user's identifier such as his or her machine log-in identification may be associated with two or more resource sharing aliases. As a result, two or more resource sharing sessions can be established by the user with a single remote host, with each of the sessions using a different one of the aliases. The resource sharing sessions are usually established in accordance with a resource sharing protocol such as the Server Block Message (SBM) protocol.

An apparatus and method control a connection between peripheral devices in a control server of a wireless communication system providing an IP-based communication service. The method for controlling the connection between peripheral devices includes registering at least one device in a group list classified by user identification information. The method also includes, if a control node including a user identifier of the group list requests a control of any one device included in the group list, checking an IP address of the device that is requested to be controlled by the control node. The method further includes sending a control command of the control node using the IP address.

A radio paging selective receiver determines that a received message is unread based on the time difference between the message reception time and the current time being larger that some predetermined value of time, and the paging selective receiver provides an indication of the unread message by displaying the reception time of the unread message in a second fashion which is visibly different from a first fashion normally used to display the current time.

A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset. A class variable may be associated with storage devices of a stripeset to identify the type of data that the stripeset can store. The class variable may be increased (or otherwise modified) when a computer stores data of a different class in the stripeset.

Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

A data processing entity that includes a mass memory with a plurality of memory locations for storing memory blocks. Each of a plurality of software images includes a plurality of memory blocks with corresponding image addresses within the software image. The memory blocks of software images stored in boot locations of a current software image are relocated. The boot blocks of the current software image are stored into the corresponding boot locations. The data processing entity is booted from the boot blocks of the current software image in the corresponding boot locations, thereby loading the access function. Each request to access a selected memory block of the current software image is served by the access function, with the access function accessing the selected memory block in the associated memory location provided by the control structure.

A process is provided for recovering aliphatic monocarboxylic acids having from 4 to 11 carbon atoms from the distillation residue obtained in the oxidation of the corresponding aldehyde by means of oxygen or oxygen-containing gas mixtures in the presence of alkali metal carboxylates or alkaline earth metal carboxylates to form the corresponding monocarboxylic acid and subsequent distillation, characterized in that the distillation residue is reacted with an aqueous acid in a tube reactor and the two-phase mixture flowing out from the tube reactor is introduced into a settling vessel in which the organic phase which separates out has a pH of 4.5 or less.