As associative thickener obtainable by free radical polymerization, the preparation thereof and the use thereof in paper coating slips are described. The associative thickener is formed from (a) acid monomers selected from ethylenically unsaturated C3- to C8-carboxylic acids, (b) associative monomers of the general formula H2C═CR1—COO-(EO)n—(PO)m—R2, in which R1 is hydrogen or methyl, n is a number of at least two, m is a number from zero to 50, EO is an ethylene oxide group, PO is a propylene oxide group and R2 is a C8-C30-alkyl group or a C8-C30-alkaryl group, and (c) nonionic, copolymerizable monomers differing from a) and b), the reaction product having been reacted, after the polymerization, with initiators forming nonionic radicals.

The present invention provides dye mixtures containing at least one dye of formula (I) and at least one dye of formula (II) where T1, T2, R1 to R9 and n are each as defined in claim 1, processes for their preparation and their use.

A bluing composition concentrate comprises an aqueous medium and at least one colorant that exhibits a blue or violet shade when deposited onto a textile material. The concentrate can be used to produce a bluing composition, and the bluing composition can be used to treat textile materials in such a way as to decrease the visually-perceived yellow coloration of textile articles that can occur with repeated use and laundering.

The present invention relates to a cosmetic composition for dyeing keratin fibers, in particular human keratin fibers such as the hair, comprising: a) one or more fatty substances; b) one or more surfactants; c) one or more oxidation bases; d) one or more couplers based on 2-hydroxynaphthalene derivatives or particular phenol derivatives, acylaminophenol derivatives or quinoline derivatives; f) one or more basifying agents; e) optionally one or more chemical oxidizing agents; and the fatty substance content representing in total at least 25% by weight relative to the total weight of the formulation. The present invention also relates to a process using this composition, and to a multi-compartment device that is suitable for performing the said process.

The present invention relates to a hair dye composition, and more particularly, to a foam-type hair dye composition comprising: a first agent including a dye and an alkaline agent and a second agent including an oxidant; and a nonionic viscosity increasing agent of a PEG-aliphatic acid ester or a PPG-aliphatic acid ester in one or both of the first agent and the second agent, thereby largely improving dyeing properties without dripping after the composition is coated on hair.

Concentrated cleaning formulations for removing debris from hard surfaces and textile surfaces. An exemplary formulation includes a mixture of the following chemical components, in specified proportions: glycerin;monopropylene glycol;triethylene glycol methyl ether;a non-ionic surfactant;an emulsifier;soya methyl ester or canola methyl ester, or both; andhydroxypropyl sulfonate; The formulation is free of water other than insignificant amounts present in the chemical components combined to make the mixture. Combining the formulation with water causes a temperature of the combination to increase above the temperatures of the water and the formulation before combining.

A control method of a laundry machine is disclosed. The control method of a laundry machine comprising a balancer includes an unbalance sensing step, wherein the unbalance sensing step recognizes an unbalancemaximum value and an unbalanceminimum value of an unbalance wave and the unbalance sensing step determines an average value of the two unbalance maximumvalue and unbalanceminimum value to be of the unbalance generated in a drum provided in the laundry machine.

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An electrical circuit includes: at least one inductor, at least one varactor, and at least two transistors, all of which electrically arranged to form a voltage controlled oscillator (VCO) having an oscillation frequency; wherein the at least two transistors includes a first transistor and a second transistor; wherein the first transistor has a first bulk terminal and a first parasitic diode disposed between the first bulk terminal and the first transistor; wherein the second transistor has a second bulk terminal and a second parasitic diode disposed between the second bulk terminal and the second transistor; wherein application of a first control voltage to the first bulk terminal, application of a second control voltage to the second bulk terminal, or application of first and second control voltages to the first and second bulk terminals, respectively, is effective to change the oscillation frequency of the VCO.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A solid state power control apparatus includes: (a) at least one IGBT and at least one FET, for supplying current to a load, and (b) a current controller for shutting off the IGBT and FET. The current controller is arranged to start shut off of the IGBT before it starts shut off of the FET. Further, the current controller is arranged to reduce current flow prior to start of the turn off of the IGBT and FET.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

In some embodiments, a phase-locked loop (PLL) system comprises a phase-frequency detector (PFD) configured to compare a phase-frequency reference signal and a feedback signal, a charge pump (CP) electrically coupled to the PFD and configured to produce a first tuning signal based on an output of the PFD, multiple integrator cells electrically coupled to the CP and configured to output multiple second tuning signals based on a voltage of the first tuning signal relative to a voltage reference signal, and a voltage-controlled oscillator (VCO) electrically coupled to the CP and to the multiple integrator cells and configured to adjust a capacitance value of the VCO based on the multiple second tuning signals. The capacitance value and the first tuning signal affect a frequency of the feedback signal.

A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

The present invention is directed to an electronic switch device, the device including a housing assembly including a front cover assembly having a user accessible surface, a back body assembly, terminals configured to be coupled to an AC power source and the load; an antenna assembly including an antenna substrate disposed inside the housing assembly adjacent a portion of the front cover assembly, an antenna being disposed on the antenna substrate having a conductive grid structure; and a circuit assembly disposed inside the housing assembly coupled to the terminals, the circuit assembly comprising a printed circuit board, the printed circuit board including a ground plane, the circuit assembly being electrically connected to the antenna assembly via a conductor, the printed circuit board being separated from the antenna assembly by a predetermined distance, the circuit assembly including a relay switch having at least one solenoid winding connected to the circuit assembly and a set of contacts.

A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A system includes a SiC semiconductor power device; a power supply board that is configured to provide power to a first gate driver board via a connector; the first gate driver board that is coupled and configured to provide current to the SiC semiconductor power device, wherein the first gate driver board is coupled to the power supply board via the connector, and wherein the first gate driver board is separated from the power supply board; and an interconnect board that is coupled to the first gate driver board, wherein the interconnect board is configured to couple the first gate driver board a second gate driver board.

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

Methods and systems include constructing and operating a semiconductor device with a mid-band dopant layer. In various implementations, carriers that are optically excited in a mid-band dopant region may provide injection currents that may reduce transition times and increase achievable operating frequency in a bipolar junction transistor (BJT). In various implementations, carriers that are optically excited in a mid-band dopant region within a thyristor may improve closure transition time, effective current spreading velocity, and maximum rate of current rise.

A nonaqueous electrolyte secondary battery of the present invention includes a positive electrode containing olivine-structured Fe or a Mn-containing phosphorus compound as a positive electrode active material; a negative electrode containing a titanium-containing metal oxide capable of inserting and extracting lithium ions as a negative electrode active material; a nonwoven fabric separator, which contains an electrically insulating fiber and is bonded to a surface of at least one of the positive electrode and the negative electrode; and a nonaqueous electrolyte. In a thickness direction of the nonwoven fabric separator, a density of the fiber on a side having contact with the positive electrode is high, and a density of the fiber on a side having contact with the negative electrode is low.

The present invention provides a nonaqueous electrolyte secondary battery separator that achieves an excellent rate characteristic by having a tensile creep compliance J satisfying at least one of the following three conditions in a case where stress of 30 MPa is applied for t seconds: (i) when t=300 seconds, J=4.5 GPa−1 to 14.0 GPa−1, (ii) when t=1800 seconds, J=9.0 GPa−1 to 25.0 GPa−1, (iii) when t=600 seconds, J=12.0 GPa−5 to 32.0 GPa−1.

A secondary battery includes a case composed of a metal containing aluminum as a main component, a stacked electrode assembly arranged in the case, a negative electrode current collector electrically connecting negative electrodes of the stacked electrode assembly to a negative electrode terminal, a positive electrode current collector electrically connecting positive electrodes of the stacked electrode assembly to a positive electrode terminal, a first metal plate arranged between the case and the stacked electrode assembly, and a spacer arranged between the case and the first metal plate, the spacer being composed of an insulating material. The positive electrodes are electrically connected to the case or a second metal plate arranged on the first metal plate with an insulating member provided between the first metal plate and the insulating member. The negative electrode current collector is in contact with the first metal plate to establish electrical connection between the negative electrode current collector and the first metal plate.

A secondary battery is disclosed. In one aspect, the secondary battery includes a case accommodating an electrode assembly, a cap plate sealing an opening of the case, an electrode terminal electrically connected to the electrode assembly and disposed over the cap, and an insulating member provided between the cap plate and the electrode terminal and configured to insulate the electrode terminal from the cap plate. The battery also includes a connection tab disposed over the electrode terminal, and a safety device having a portion positioned under the connection tab and electrically connected to the electrode terminal via the connection tab. The safety device has at least one of electric conductivity and thermal conductivity greater than that of the connection tab, and at least a part of the safety device is seated on the insulating member.

The object of the present invention is to provide a positive electrode active material usable for a lithium ion battery capable of high charge/discharge cycle performance and high discharge capacity. The positive electrode active material for a lithium secondary battery has a layered structure and comprises at least nickel, cobalt and manganese. Further, the positive electrode active material satisfies requirements (1) to (3) below: (1) a primary particle size of 0.1 μm to 1 μm, and a 50% cumulative particle size D50 of 1 μm to 10 μm, (2) a ratio (D90/D10) of volume-based 90% cumulative particle size D50 to volume-based 10% cumulative particle size D10 of 2 to 6, and (3) a lithium carbonate content in a residual alkali on particle surfaces of 0.1% by mass to 0.8% by mass as measured by neutralization titration.

The positive electrode as an embodiment includes a positive electrode current collector mainly composed of aluminum, a positive electrode mixture layer containing a lithium-containing transition metal oxide and disposed above the positive electrode current collector, and a protective layer disposed between the positive electrode current collector and the positive electrode mixture layer. The protective layer contains inorganic particles, an electro-conductive material, and a binding material; is mainly composed of the inorganic particles; and is disposed on the positive electrode current collector to cover the positive electrode current collector in approximately the entire area where the positive electrode mixture layer is disposed and at least a part of the exposed portion of the positive electrode current collector where the positive electrode mixture layer is not disposed on the surface of the positive electrode current collector.

The present invention relates to a positive electrode active material for a sodium secondary battery, and a method for preparing the same. The positive electrode active material for the sodium secondary battery according to the present invention is structurally more stable by replacing a part of the transition metal with Li, and accordingly, the thermal stability and life characteristics of the sodium battery including the positive electrode active material are greatly improved.

A carbon material for a non-aqueous secondary battery containing a graphite capable of occluding and releasing lithium ions, and having a cumulative pore volume at pore diameters in a range of 0.01 μm to 1 μm of 0.08 mL/g or more, a roundness, as determined by flow-type particle image analysis, of 0.88 or greater, and a pore diameter to particle diameter ratio (PD/d50 (%)) of 1.8 or less, the ratio being given by equation (1A): PD/d50 (%)=mode pore diameter (PD) in a pore diameter range of 0.01 μm to 1 μm in a pore distribution determined by mercury intrusion/volume-based average particle diameter (d50)×100 is provided.

Disclosed is an anode for a molten carbonate fuel cell (MCFC) having improved creep property by adding an additive for imparting creep resistance to nickel-aluminum alloy and nickel as materials for an anode. Improved sintering property, creep property and increased mechanical strength of a molten carbonate fuel cell may be obtained accordingly.

One embodiment includes a method comprising the steps of providing a first dry catalyst coated gas diffusion media layer, depositing a wet first proton exchange membrane layer over the first catalyst coated gas diffusion media layer to form a first proton exchange membrane layer; providing a second dry catalyst coated gas diffusion media layer; contacting the second dry catalyst coated gas diffusion media layer with the first proton exchange membrane layer; and hot pressing together the first and second dry catalyst coated gas diffusion media layers with the wet proton exchange membrane layer therebetween.

A catalyst composition and a use thereof are provided. The catalyst composition includes a support and at least one RuXMY alloy attached to the surface of the support, wherein M is a transition metal and X≧Y. The catalyst composition is used in an alkaline electrochemical energy conversion reaction, and can improve the energy conversion efficiency for an electrochemical energy conversion device and significantly reduce material costs.