A sheet processing apparatus which is capable of completing a bound document containing appropriately Z-folded sheets when performing folding together with edge cutting and binding. The sheet processing apparatus controls a Z-folding process, a cutting process, and a binding process for a sheet. A first folding position from a free end of the sheet coincides with a position corresponding to half a width of the sheet excluding a cut width of the sheet a binding margin, when the Z-folding process, the cutting process, and the binding process are executed.

A supply device (10) for a machine for transversely cutting two strips (11 and 12) of a flexible material, in particular a strip of paper, moving continuously, to produce separate stacks of documents cut transversely according to predetermined formats. The device comprises lower and upper driving mechanisms (13, 14) associated with the two strips (11, 12) of flexible material respectively, which each include a mechanically rotated first roller (13a, 14a) and a freely rotatable second bearing roller (13b and 14b). The driving mechanism is mounted on a frame (15) supported by a movable platform (16) which is rigidly connected to a linear actuator (17) arranged to be moved transversely with respect to the direction of movement of the strips (11 and 12). Optical reading cells (11a, 11b, 12a, 12b) define the operating modes of the driving servomotors (13b and 14b) and of the linear actuator (17).

A method of producing a print product comprises: performing digital printing of each surface of the print product, sequentially and repeatedly, on a continuous paper; forming a section by cutting the printing-completed continuous paper into a paper sheet and folding the paper sheet in two; forming a section block by at least one of sections; and folding the section block in two.

In a first step, in a printed material web (1) moved in a feed direction, a first material web part (5) which is formed by a material web section (1a)is folded against the rest of the material web (6) that is formed from two material web portions (1b, 1c)).In the region of a connecting line (2b) extending between neighbouring material web sections (1b, 1c) the two material web parts (5,6) are connected to one another by a means of a bonding adhesive. In a subsequent step the material web (1) is folded again along a line (2b) extending between two neighbouring material web sections. (1b, 1c)All material web sections (1a, 1b, 1c) lie above one another. Subsequently, multi-page sub-products (11), the pages (12a, 12b, 12c) of which are connected to one another in the region of the spine (13) of the sub-product, are separated from the twice-folded material web (1). Finally, the sub-products (11) are placed on top of one another to form a stack (16) and are connected to one another in the region of the spine (13) thereof by means of a bonding adhesive.

In an embodiment, a processor-readable medium stores code representing instructions that when executed by a processor cause the processor to receive sheet length data for two paper sheets of a same standard dimension passing consecutively through a printing device. The processor calculates a length difference between the two paper sheets, and when the length difference exceeds a two-sheet threshold, it initiates an alignment correction cycle in a paper finishing device.

This invention provides a technique of preventing a collision between an original document and a printing material on a conveyance path when an image forming apparatus executes both additional printing on the original document and printing on the printing material. In a case where both additional printing on an original document and printing on a printing material are executed, the image forming apparatus according to one aspect of the invention conveys a read original document to a transfer unit through a conveyance path commonly used for an original document and sheet, and prints an image to be added on the original document. After the original document is conveyed to the transfer unit through the conveyance path, the image forming apparatus feeds a sheet from a sheet feeding unit to the conveyance path, and performs copying on the sheet in the transfer unit.

A printing control apparatus according to one aspect of this invention controls to print images on sheets based on image data of a plurality of pages, generate a bookbinding product by executing folding processing for the image-printed sheets, and output the bookbinding product. The printing control apparatus further accepts the position of an insertion sheet to be inserted into the sheets for which the folding processing is executed, and controls to output a plurality of bookbinding products by using, as a reference, the accepted position of the insertion sheet.

A sheet binding apparatus which forms concavity and the convexity on a sheet bundle including a plurality of sheets in a thickness direction so as to bind the sheet bundle, the sheet binding apparatus includes: a pair of concave-convex members, each of which has concave-convex portion in the thickness direction of the sheet bundle and which forms the concavity and the convexity on the sheet bundle in the thickness direction while niping the sheet bundle therebetween; wherein in the pair of concave-convex members, one of the concave-convex members has a greater difference in height of the concave-convex portion than that of the other concave-convex member which engages with the above-described concave-convex member.

The present invention is directed to providing a mechanism for allowing a user to easily take out print products discharged onto a plurality of sheet discharge trays in the discharge order. A control method for controlling a sheet processing apparatus for performing control to discharge sheets onto a plurality of sheet discharge trays includes storing, in a storage unit, the discharge order in which sheets have been discharged onto equal to or more than two sheet discharge trays by executing a job, and performing, upon reception of a take-out instruction for taking out in the discharge order the sheets discharged by executing the job, processing for allowing a user to take out the sheets discharged onto the equal to or more than two sheet discharge trays, in the discharge order stored in the storage unit.

An image recording apparatus includes: a recording unit for recording an image on a recording medium; a tray for supporting the recording medium recorded by the recording unit; a conveyor mechanism for conveying the recorded medium to the tray; and an alignment mechanism for aligning a plurality of recording media stacked on the tray, by application of an external force. In a period from a start to an end of recording based on one recording job, the alignment mechanism aligns the plurality of recording media stacked on the tray in a period in which image recording is not performed, and the alignment mechanism does not align the plurality of recording media stacked on the tray in a period in which image recording is being performed.

A sheet processing apparatus and a method of controlling the same align sheets stacked on a stacking unit, by causing a first alignment member and a second alignment member to come into contact with edges of a sheet stacked on the stacking unit in a sheet width direction. In a case that a second sheet that is different from a first sheet stacked on the stacking unit is to be stacked on the first sheet and aligned using the first alignment member and the second alignment member, control is performed to discharge a partition sheet onto the first sheet stacked on the stacking unit.

A mechanism capable of changing an upper limit number of sheets for a post-process is provided. To achieve this, a control method for controlling a sheet processing apparatus which performs the post-process for the sheets on which images are formed, comprising: storing, in a storage unit, the upper limit number of sheets to which the post-process can be performed; and changing the upper limit number of sheets stored in the storage unit is provided.

To provide a sheet storage apparatus for enabling sheets that are carried out of an image formation apparatus or the like on the upstream side to be loaded and stored in a predetermined position with a correct posture neatly at high speed, a sheet discharge roller and a reverse roller spaced a distance are disposed in a sheet discharge outlet and a tray, a kick member is provided to be swingable in a vertical direction passing a sheet discharge path of a sheet discharged from the sheet discharge outlet, and a posture of the kick member is controlled by shift means. The shift means controls the kick member among a waiting posture retracted upward from the sheet discharge path, an engagement posture for imposing a load on the sheet to engage, and an actuation posture dropping onto the tray together with the sheet.

A multi-function binding machine is proposed. The multi-function binding machine (700) comprises a binding station (135) for binding blocks of signatures (105), and a feeding station (115) for receiving signatures in succession, opening the signatures, and feeding the signatures to the binding station; in the solution according to an embodiment of the invention, the multi-function binding machine further comprises a further feeding station (715) for receiving pre-signatures in successions, folding groups of at least one pre-signature into further signatures (729), and feeding the further signatures to the binding station.

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.

Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A light emitting element array for an illumination apparatus, an illumination apparatus and method of manufacture of the same in which an array of light-emitting elements and an array of light directing optics are provided between first and second attached mothersheet substrates wherein the thermal resistance of at least one of the mothersheet substrates is reduced by means of thickness reduction so as to provide reduced LED junction temperature.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

The present invention provides an electroconductive sheet and a touch panel which do not impair visibility in a vicinity of an electrode terminal in a sensing region. In an electroconductive sheet which has an electrode pattern constructed of a metal thin wire and an electrode terminal that is electrically connected to an end of the electrode pattern, a transmittance of the electrode pattern is 83% or more, and when the transmittance of the electrode pattern is represented by a %, a transmittance of the electrode terminal is controlled to be (a-20)% or more and (a-3)% or less.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.