To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

A semiconductor device that includes transistors having the same polarity consumes less power and can prevent a decrease in amplitude of a potential output. The semiconductor device includes a first wiring having a first potential, a second wiring having a second potential, a third wiring having a third potential, a first transistor and a second transistor having the same polarity, and a plurality of third transistors for selecting supply of the first potential to gates of the first transistor and the second transistor or supply of the third potential to the gates of the first transistor and the second transistor and for selecting whether to supply one potential to drain terminals of the first transistor and the second transistor. A source terminal of the first transistor is connected to the second wiring, and a source terminal of the second transistor is connected to the third wiring.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

A stage circuit including an output unit for supplying first or second power source to an output terminal is disclosed. The stage circuit may comprise a bidirectional driver for respectively supplying signals supplied to first and second input terminals, a first driver, and a second driver. The second driver controls the output unit to output the second power source to the output terminal without any voltage loss, corresponding to a second clock signal.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A vehicle restraint system includes a strap assembly configured to be positioned on a portion of a tire of a vehicle to secure the vehicle to a deck of a transport. The strap assembly is also configured to be coupled to the deck of the transport on a first side of the tire of the vehicle. The system also includes a mandrel assembly operable to be coupled to the strap assembly on a second side of the tire of the vehicle, opposite the first side. The system further includes a winch assembly configured to be coupled to the deck of the transport and the mandrel assembly on the second side of the tire of the vehicle, the winch assembly configured to rotate the mandrel assembly to produce a tightening force to tighten the strap assembly around the portion of the tire. The system still further includes a release mechanism disposed between the winch assembly and the mandrel assembly and configured to create a coupling between the winch assembly and the mandrel assembly in a manner that transmits the tightening force from the winch assembly to the mandrel assembly. The release mechanism is configured to release the coupling between the winch assembly and the mandrel assembly when a force greater than or equal to a predetermined force is produced against the release mechanism.

A transportation and storage system for a wind turbine rotor blade comprises a tip end frame assembly comprising a tip end receptacle and a tip end frame. The tip end receptacle comprises an upwardly open tip end-receiving space for receiving a portion of the tip end of the blade and having a supporting surface for supporting the blade, a lower surface allowing the tip end receptacle to rest upright on a substantially horizontal surface, such as the ground, and releasable retaining means for releasably retaining the tip end of the blade in the receiving space of the tip end receptacle. The tip end frame comprises an upwardly open receptacle-receiving space for receiving the receptacle and provided with positioning means for positioning the receptacle in the tip end frame. A base part defines a bottom surface allowing the tip end frame to rest upright on the ground.

A pallet system includes a pallet upon which cargo or other payloads may be carried. The pallet has a plurality of tie-down locations at which the pallet may be tied-down on a base, and at least one tie-down device for tying down the pallet on the base at any of the tie-down locations. The pallet further includes structure for mounting the tie-down device on the pallet at any of the tie-down locations.

Some embodiments of the invention relate to function elements for fixing in seat rails of aircraft. The function element according to the invention may include: a fixing rail with a web running in the x direction and a multiplicity of extensions which protrude beyond the web in a y direction to form a T profile, wherein the fixing rail is formed corresponding to the seat rail such that the fixing rail can be inserted in the seat rail and moved along the x direction into a holding position in which the extensions sit between the holes below the slots, at least one fixing peg which is arranged mobile on the fixing rail and can be brought into a blocking position in which the fixing peg engages in a hole of the seat rail so that the function element is fixed in the x direction.

An improved e-track connector, or lockdown, is presented that can be installed in single locations instead of provided in tracks as in the industry. It also possesses a finished slot that accepts logistics straps buckles. The slot is a complete rectangle with no excess material folded under it and has been deburred and finished smooth. The device also possesses a drain slot along the side of the tang and drain holes in the buckle receiver such that liquid will drain out of the connector when it is mounted horizontally.

An extendable, intermodal transport platform is disclosed. The invention comprises a standard ISO-length loading platform supported by main beams and crossmembers. The platform has ISO lifting and stacking fitments at its four corners. The platform has extendable supplemental platforms at each end, the extendable supplemental platforms fitting beneath the deck bed of the platform, or extendable to position stacking fitments at over-the-road trailer positions for North American fleet. Inner stacking fitments may laterally expand and retract so as to slide underneath the deck bed between the main beams. In some embodiments the platform includes posts that extend upward to position ISO lifting fitments at standard heights, such as under hydraulic power.

An example wheel restraint includes a track to be positioned adjacent a vehicle approach path of a loading dock. A shuttle is pivotally coupled to the track via a track follower and pivots between a home position and a deployed position about a shuttle axis substantially parallel to and offset relative to a longitudinal axis of the track. A barrier is pivotally coupled to the shuttle and pivots between a non-blocking position and a blocking position about a pivot axis substantially parallel to and spaced apart from the longitudinal axis of the track such that the shuttle rotates in a first direction about the shuttle axis when the shuttle moves from the home position to the deployed position and bather rotates in a second direction about the pivot axis when the barrier moves from the non-blocking position to the blocking position, where the first direction being different than the second direction.

An automatic lock affixed to a cargo container for interconnecting two stacked containers, and for automatically locking and unlocking without reliance upon the overcoming of a friction force to release the device.

A box stop device includes a base member and a raised member attached to the base member. The base member has a top surface and a bottom surface. The top surface may be flat. The bottom surface may be adapted to attach to a desired surface. The raised member may be attached to the base member and may extend approximately vertically from the top surface. The raised member may include a first side and a second side. The first side and the second side may be attached together at an angle of approximately 90 degrees.

A module in the form of a pallet or a closed container includes a grouping together of the electrical devices in an avionics bay, in which the electrical devices are interconnected and attached so as to facilitate the mounting and thus limit the time it takes to mount the electrical devices in the avionics bay.

An apparatus for selectively securing a boat to a trailer may include a hull contact structure for abutting against the boat hull, and a releasable gripping structure positioned adjacent the hull contact structure to engage the boat's securing loop and selectively lock onto the loop to hold the boat to the trailer.

A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.

An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.

Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.