The country’s clothes manufacturers are taking a beating from imported ‘preloved’ clothes and a struggling economy.

Innovative professional development initiatives infuse technology with in-person learning to enhance learning experiences for teachers.

Midfielder Matias Harte, of State College, was named the AMCC’s Offensive Player of the Week, and defender Owen Myers, of Spring Grove, was selected the conference’s Defensive Player of the Week.

Attendees were invited to read or perform their own work or music or share a favorite piece of poetry or prose. The event began with a reading by English professors Todd Davis and Erin Murphy.

A poetry reading by Mike Simms will take place from 12:05 to 1:20 p.m. on Thursday, Nov. 14, in the Titelman Study of the Misciagna Family Center for Performing Arts at Penn State Altoona. Simms is a poet, novelist, essayist, political activist, editor and publisher.

Penn State Altoona’s Ivyside Dance Ensemble will present its fall 2024 performance at 7:30 p.m. Nov. 14-15 in the Wolf Kuhn Theatre of the Misciagna Family Center for Performing Arts. The performance will consist of seven dances from director KT Huckabee, choreographer and instructor Jaye Mackinson, and returning guest choreographer Ana Rossi-Lanzendorfer.

Join Penn State Altoona as it kicks off Veteran Appreciation Week with a community movie night on Saturday, Nov. 9, at the Devorris Downtown Center in downtown Altoona. The first family-friendly movie, “Hotel Transylvania,” will begin at 5:30 p.m. The second adult-themed movie is “Pineapple Express,” which will begin between 7:30 and 8 p.m.

Patricia Jabbeh Wesley, professor of English at Penn State Altoona, will be featured in the 55th annual Poetry International Festival in the Netherlands. The event will take place June 12 through 15, 2025.

Penn State Altoona faculty members Brian Onishi, associate professor of philosophy, and Jeff Stoyanoff, assistant professor of English and women's, gender, and sexuality studies, released a new episode of their podcast, “Horror Joy,” titled “Appalachian Folk Horror: ‘The Blair Witch Project’ and ‘Old Gods of Appalachia.’”

Five Penn State Altoona criminal justice students participated in the third annual Federal Mock Sentencing Exercise at the United States District Court for the Western District of Pennsylvania in Johnstown on Thursday, Oct. 24.

Brian Black’s newest book, “Ike’s Road Trip: How Eisenhower’s 1919 Convoy Paved the Way for the Roads We Travel,” has received a full review by Mark Yost for the Wall Street Journal.

Student Rebecca Reeder and faculty members Danielle DelPriore, Kyle King, and Lindsey Lilienthal will present “Nuisance Variable: An Undergraduate Journey in Research” as part of the Spotlight on Teaching and Research (STAR) lecture series.

World Kindness Day is Wednesday, Nov. 13, but at Penn State Altoona, we are celebrating all week. Events include a friendship-themed Taco Tuesday, sweet treats, and displays of affirmations on Kindness Trees throughout campus.

Penn State Altoona student-athlete Eugene Heyman, of Boiling Springs, was selected as the Allegheny Mountain Collegiate Conference’s Men’s Swimmer of the Week on Monday, Nov. 11, when the league office announced its weekly awards. Heyman had two individual first-place finishes and also was part of a relay first place in the Lions’ sweep of conference opponents Alfred State College and Pitt-Bradford.

Penn State Altoona goalkeeper Sasha Mohoruk, of State College, and defender Owen Myers, of Spring Grove, were both voted to the All-Allegheny Mountain Collegiate Conference team in men’s soccer, the league office announced on Tuesday, Nov. 12.

Virtual reality goggles with a choice of soothing environments or guided meditations, a color-changing bubble wall, a prayer area, Zen garden and massage chair: These are all options provided by Penn State Wilkes-Barre’s Counseling Services to help students relax and stay calm.

OM workers in the Arabian Peninsula testify to healing and deliverance miracles amongst Muslims.

Sewage surveillance is emerging as a crucial method in combating antimicrobial resistance (AMR), according to new research from Virginia Tech. Published in Nature Water, the study demonstrates that monitoring wastewater provides a more efficient and comprehensive approach to tracking antibiotic-resistant bacteria than testing individuals. This method holds particular promise for underserved communities, where access to healthcare is limited, and AMR-related diseases are most prevalent. The research team, led by experts such as Dr. Leigh-Anne Krometis and Dr. Marc Edwards, explored sewage samples from 62 countries and found significant correlations between AMR levels and socioeconomic factors, such as healthcare accessibility. By examining wastewater, public health officials could gain early insights into AMR spread, allowing them to take targeted actions to protect vulnerable populations. This approach could revolutionise AMR monitoring, particularly in rural and low-income areas, where AMR poses a growing threat.

Google released a new experimental artificial intelligence (AI) tool on Monday aimed at helping users learn about new topics. Dubbed Learn About, the tool is different from the Mountain View-based tech giant's usual AI offerings, such as Gemini or AI Overviews. The experimental tool shows the information in a visual and interactive style and picks the data from educational sources.

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Thursday August 26, 2021 Dover, DE – Delaware Libraries are pleased to announce the launch of Northstar Digital Literacy, an online training tool for basic computer skills. Northstar Digital Literacy provides digital literacy assessments and tutorials in basic computer skills and tips for how to use technology in daily life. Delaware Libraries and Literacy Delaware […]

DOVER (Dec. 10, 2021) – On Thursday, Dec. 9,  2021, the Delaware Division of Public Health (DPH) ordered a Millsboro man to cease tattooing activities in his home, in violation of Title 16 of the Delaware Code. Body art activities should only be performed in DPH-permitted facilities. Private residences are not properly equipped for these activities to […]

DOVER, DE (Dec. 21, 2021) – The Delaware Division of Public Health (DPH) announced today that individuals vaccinated in Delaware will now have access to a QR code when downloading their COVID-19 vaccination record. The digital COVID-19 vaccination card now includes the QR code and is available through the DelVAX Public Portal, a site where those who were […]

DNREC announced today the 2025 Community Environmental Project Fund (CEPF) grants will have a focus on equity. This change comes after the CEPF grant process was revamped to better address community needs and strengthen partnerships.

The Supreme Court on Tuesday extended the interim protection from arrest granted to Malayalam film actor Siddique in an alleged rape case.

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Read the in depth Review of Mi Neckband Bluetooth Earphones Pro Audio Video. Know detailed info about Mi Neckband Bluetooth Earphones Pro configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Mi Portable Bluetooth Speaker (16W) Audio Video. Know detailed info about Mi Portable Bluetooth Speaker (16W) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

On February 4, 2019, gloom settled over the iconic Brigade Parade grounds in the heart of Kolkata. Kanhaiya Kumar, then a firebrand Left leader known for his rousing speeches, had cancelled his visit to a rally just before the Lok Sabha election

Your sweet tooth could depend on your ability to digest sugar  BBC Science FocusView Full coverage on Google News

[GroundUp] Former Lavender Hill gangster died on 29 October

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

Hi all, 

I have made a custom cell in Innovus that I will be instantiating into a bigger block, which I will also be using Innovus to do the Place & Route. 

I understand that I can generate a *.lef file and a *.lib file using Innovus. However, I need to also create a *.db file (these format of files are often used in DC Compiler synthesis tool). 

Is there a way to create the *.db file from Innovus? Or, is there a tool that I can use to create this *.db file? 

Thank you for your time. 

Disappearing toolbar or docked menu

Is there a way for the toolbar or floating menu from disappearing when a cells tab is added to a window?

I have created a skill toolbar and it disappeared when I add another cell or tab to a window.

The only toolbars that stay are the ones I have defined in the Layout.toolbar file.

Do I have to add a trigger to keep the toolbars visible or not disappearing from the window?

Cadence version IC23.1-64b.ISR7.27

Paul

We are looking for suitable tools that could be used for RTL design, IP-XACT based  integration (third party IP) and RTL design verification ( SV / UVM based methodology).

Request to share details on the different Cadence tools that is most suitable for these activities.

I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design Engineer, I want to make sure that if another tool has the capability of doing Linting earlier in the flow. for example, does Xcelium, Genus or Confomal support linting. I have seen some contradicting information online regarding this topic, though I can't find anything related to Linting on any of these tools.

Thanks

Hi,

Current and valid TCAs for Functional Safety are readily available at the FuSa "one-stop shop".

But I have not been able to find any archive repository for access to the obsoleted versions.

I would need to have also v1.4 of Xcelum TCA to investigate exact changes wrt previous projects.

Anyone knows how to find it?

Best regards,  Lars

Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution, and Quantus Extraction Solution—Socionext achieved remarkable improvements.

Notably, the Tempus DSTA tool dramatically cut timing closure time by 73%, outperforming conventional single-machine STA methods. This achievement, combined with the synergistic use of Cadence's Certus Closure and Tempus Timing solutions, allowed Socionext to meet their ambitious three-day iteration target and double productivity. Additionally, integrating these solutions significantly decreased both human and machine resource needs, slashing memory and disk costs by up to 90% and halving engineering resources during the optimization and signoff phases.

For more on this collaboration, check out the "Designed with Cadence" success story video on Cadence's website and YouTube channel.

Also, don't miss the on-demand webinar "Fast, Accurate STA for Large-Scale Design Challenges," which provides a deeper dive into Socionext's breakthroughs and the innovative solutions that powered their success.

Our top picks, at a glance: The Ultimate Ears Wonderboom 4 for $79.99 (save $20), the Sony XG300 for $199.99 (save $150), and the Anker Soundcore Motion 300 for $59.99 (save $20).

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Robotics developers can greatly accelerate their work on AI-enabled robots, including humanoids, using new AI and simulation tools and workflows that NVIDIA revealed this week at the Conference for Robot Learning (CoRL) in Munich, Germany. The lineup includes the general availability of the NVIDIA Isaac Lab robot learning framework; six new humanoid robot learning workflows Read Article

The NVIDIA app — officially releasing today — is a companion platform for content creators, GeForce gamers and AI enthusiasts using GeForce RTX GPUs.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

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