By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

A method and apparatus for method of continuously producing 1,1,1,2,3-pentafluoropropane with high yield is provided. The method includes (a) bringing a CoF3-containing cobalt fluoride in a reactor into contact with 3,3,3-trifluoropropene to produce a CoF2-containing cobalt fluoride and 1,1,1,2,3-pentafluoropropane, (b) transferring the CoF2-containing cobalt fluoride in the reactor to a regenerator and bringing the transferred CoF2-containing cobalt fluoride into contact with fluorine gas to regenerate a CoF3-containing cobalt fluoride, and (c) transferring the CoF3-containing cobalt fluoride in the regenerator to the reactor and employing the transferred CoF3-containing cobalt fluoride in Operation (a). Accordingly, the 1,1,1,2,3-pentafluoropropane can be continuously produced with high yield from the 3,3,3-trifluoropropene using a cobalt fluoride (CoF2/CoF3) as a fluid catalyst, thereby improving the reaction stability and readily adjusting the optimum conversion rate and selectivity.

A solvent that reversibly converts from a hydrophobic liquid form to hydrophilic liquid form upon contact with water and a selected trigger, e.g., contact with CO2, is described. The hydrophilic liquid form is readily converted back to the hydrophobic liquid form and water. The hydrophobic liquid is an amidine or amine. The hydrophilic liquid form comprises an amidinium salt or an ammonium salt.

A composition and method demulsify a produced emulsion from anionic surfactants and polymer (SP) and alkali, surfactants, and polymer (ASP). The produced emulsion is demulsified into oil and water. In one embodiment, the composition includes a surfactant. The surfactant comprises a cationic surfactant, an amphoteric surfactant, or any combinations thereof.

Emulsions, and processes for making the emulsions, useful for imparting water resistance to gypsum products are disclosed. Process for making the emulsion and gypsum products made from the emulsion are also disclosed. The emulsions of the invention include at least one paraffin wax and a hydrophilic metallic salt. The emulsions of the invention may further include a saponifiable wax substitute for montan wax. The emulsions of the invention may further include a biocide.

Oil-water dispersions and emulsions derived from petroleum industry operations are demulsified and clarified using anionic polymers. Formation of such oil-water dispersion and emulsions is inhibited and mitigated using the anionic polymers. The anionic polymers comprise: A) 2-80% by weight of at least one C3-C8 α,β-ethylenically unsaturated carboxylic acid monomer; B) 15-80% by weight of at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer; C) 1-50% by weight of one or more of the following monomers: C1) at least one nonionic vinyl surfactant ester; or C2) at least one nonionic, copolymerizable α,β-ethylenically unsaturated monomer having longer polymer chains than monomer B), or C3) at least one nonionic urethane monomer; and, optionally, D) 0-5% by weight of at least one crosslinker.

Emulsions, and processes for making the emulsions, useful for imparting water resistance to gypsum products are disclosed. Process for making the emulsion and gypsum products made from the emulsion are also disclosed. The emulsions of the invention include at least one paraffin wax and a hydrophilic metallic salt. The emulsions of the invention may further include a saponifiable wax substitute for montan wax. The emulsions of the invention may further include a biocide.

A method of reducing the downward flow of air currents on the leeward side of an emissions emitting structure including the step of using a system that includes components chosen from the group consisting of one or more mechanical air moving devices; physical structures; and combinations thereof to create an increase in the air pressure within a volume of air on the leeward side of an emissions emitting structure having emissions that become airborne. The increased air pressure prevents or lessens downward flow of emissions that would occur without the use of the system and increases the safety by which one can travel a road or other transportation route that might otherwise be visually obscured by the emissions and the safety of the property and those within the area where emissions occur.

An aqueous delivery system is described including at least one surfactant and at least one water insoluble wetting agent. Further described are low surface energy substrates, such as microporous polytetrafluoroethylene, coated with such an aqueous solution so as to impart a change in at least one surface characteristic compared to the surface characteristics of the uncoated low surface energy substrate.

Provided is an oil-in-water silicone emulsion composition that has a low silicone oligomer content, and that can form, even without the use of an organotin compound as a curing catalyst, a cured film that exhibits satisfactory strength and satisfactory adherence to a substrate, through the removal of water fraction. An oil-in-water silicone emulsion composition comprising (A) 100 mass parts of a polyorganosiloxane that contains in each molecule at least two groups selected from the group consisting of a silicon-bonded hydroxyl group, alkoxy group, and alkoxyalkoxy group, (B) 0.1 to 200 mass parts of a colloidal silica, (C) 0.1 to 100 mass parts of an aminoxy group-containing organosilicon compound that has in each molecule an average of two silicon-bonded aminoxy groups, (D) 1 to 100 mass parts of an ionic emulsifying agent, (E) 0.1 to 50 mass parts of a non-ionic emulsifying agent, and (F) 10 to 500 mass parts of water.

A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code. A determination section determines whether or not the computing section has stored an entry of configuration information corresponding to the status to which the computing section needs to advance the next time based on the logical status number that is output from the status management section. A rewriting section correlatively stores the entry of the configuration information and a physical configuration number corresponding to the entry of the configuration information in the computing section when the determination section determines that the computing section has not stored the entry of configuration information corresponding to the status to which the computing section needs to advance the next time.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

Methods and apparatus for client-allocatable bandwidth pools are disclosed. A system includes a plurality of resources of a provider network and a resource manager. In response to a determination to accept a bandwidth pool creation request from a client for a resource group, where the resource group comprises a plurality of resources allocated to the client, the resource manager stores an indication of a total network traffic rate limit of the resource group. In response to a bandwidth allocation request from the client to allocate a specified portion of the total network traffic rate limit to a particular resource of the resource group, the resource manager initiates one or more configuration changes to allow network transmissions within one or more network links of the provider network accessible from the particular resource at a rate up to the specified portion.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed.

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.

Systems, Apparatus, methods, and computer program products are provided for converting an existing artifact to one or more new artifacts. For example, in one embodiment, a computing device can receive input identifying an existing artifact for conversion to one or more new artifacts. One or more items from the existing artifact and their respective types can be identified for conversion. Then, the one or more items of the existing artifact can be converted to one or more new artifacts.

The disclosure generally describes computer-implemented methods, software, and systems for creating and using two-tier mobile applications. A computer-implemented method includes identifying at least a portion of a database to be associated with a mobile application, retrieving a set of metadata associated with the at least a portion of the identified database, automatically generating a set of mobile application source code for directly accessing the at least a portion of the database based on the set of retrieved metadata, and compiling the set of mobile application source code into a distributable mobile application, the distributable mobile application configured to directly access the identified database associated with the mobile application. In some instances, the identifying, retrieving, generating, and compiling operations are performed at design time, while at runtime, the mobile application is executable by a mobile device and, during runtime execution, can request database-related information directly from the identified database.

Disclosed is a novel system and method to select software components. A set of available software components are accessed. Next, one or more dimensions are defined. Each dimension is an attribute to the set of available software components. A set of coherence distances between each pair of the available software components in the set of available software components is calculated for each of the dimensions that have been defined. Each of the coherence distances are combined between each pair of the available software components that has been calculated in the set of the coherence distances into an overall coherence degree for each of the available software components. Using the overall coherence degree, one or more software components are selected to be included in a software bundle.

A method for recommending at least one artifact to an artifact user is described. The method includes obtaining user characteristic information reflecting preferences, particular to the artifact user, as to a desired artifact. The method also includes obtaining first metadata about each of one or more candidate artifacts, and scoring, as one or more scored artifacts, each of the one or more candidate artifacts by evaluating one or more criteria, not particular to the artifact user, applied to the first metadata. The method further includes scaling, as one or more scaled artifacts, a score of each of the one or more scored artifacts, by evaluating the suitability of each of the one or more scored artifacts in view of the user characteristic information. The method lastly includes recommending to the artifact user at least one artifact from among the one or more scaled artifacts based on its scaled score.

An aspect of the present invention identifies differences between source codes (e.g. of different versions of a software), when each source code is organized using incorporated files. In one embodiment, in response to receiving identifiers of a first and second source codes (each source code being organized as a corresponding set of code files), listings of the instructions in the first and second source codes are constructed. Each listing is constructed, for example, by replacing each incorporate statement in the source code with instructions stored in a corresponding one of code files. The differences between the first and second source codes are then found by comparing the constructed listings of instructions.

A system and method may generate unit tests for source code concurrently with API documentation. The system may receive a source code file including several comments sections. Each comments section may include a description of a source code unit such as a class, method, member variable, etc. The description may also correspond to input and output parameters the source code unit. The system and method may parsing the source code file to determine a source code function type corresponding to the unit description and copy the unit description to a unit test stub corresponding to the function type. A developer or another module may then complete the unit test stub to transform each stub into a complete unit test corresponding to the source code unit. Additionally, the system and method may execute the unit test and generate a test result indication for each unit test.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

Computer-implemented methods for analyzing computer programs written in semi-structured languages are disclosed. The method is based on unification of the two classic forms of program flow analysis, control flow and data flow analysis. As such, it is capable of substantially increased precision, which increases the effectiveness of applications such as automated parallelization and software testing. Certain implementations of the method are based on a process of converting source code to a decision graph and transforming that into one or more alpha graphs which support various applications in software development. The method is designed for a wide variety of digital processing platforms, including highly parallel machines. The method may also be adapted to the analysis of (semi-structured) flows in other contexts including water systems and electrical grids.

Embodiments of the present disclosure provide a method and a system for upgrading software. The method includes: a client reports a software upgrade request to a server, wherein the upgrade request carries file information of the local software to be upgraded; the server determines the difference with the latest version software according to the file information of the software to be upgraded in the upgrade request, and generates upgrade instruction information according to the difference and sends it to the client; the client downloads and updates the relevant files and performs the relevant local upgrade operations according to the instructions in received upgrade instruction information. Technical solutions of the present disclosure can save bandwidth resources and reduce the workload for upgrading software.

A binary library overload instruction is received at an embedded computing device that executes a write-protected firmware build. The binary library overload instruction specifies a write-protected binary library of the write-protected firmware build to be overloaded by execution of an alternative binary library instead of the write-protected binary library of the write-protected firmware build. The alternative binary library is configured within a random access memory (RAM) storage area to execute instead of the write-protected binary library as specified in the received binary library overload instruction. The write-protected firmware build is executed using the alternative binary library instead of the write-protected binary library specified in the binary library overload instruction.

An electronic system and method of operation thereof includes: a control unit for receiving a patterned signal; a recognizer module, coupled to the control unit, for recognizing an unique trigger from the patterned signal; an operation module, coupled to the recognizer module, for detecting an operational mode from the unique trigger; and a change module, coupled to the operation module, for configuring a system state change of a memory sub-system based on the operational mode.

A software streaming platform may be implemented that predictively chooses units of a program to download based on the value of downloading the unit. In one example, a program is divided into blocks. The sequence in which blocks of the program historically have been requested is analyzed in order to determine, for a given history, what block is the next most likely to be requested. Blocks then may be combined into chunks, where each chunk represents a chain of blocks that have a high likelihood of occurring in a sequence. A table is then constructed indicating, for a given chunk, the chunks that are most likely to follow the given chunk. Based on the likelihood table and various other considerations, the value of downloading particular chunks is determined, and the chunk with the highest expected value is downloaded.

The present invention relates generally to client-server architectures for allowing generic upload and download functionality between a web application at a server and a client. One exemplary method includes sending a download/upload request to a web application at the server, where the download/upload request specifies at least one file to download/upload; receiving a transmission from the server; parsing the transmission to identify a download/upload command and an associated download/upload manifest, where the download/upload manifest includes executable code that, when executed on the client, will perform the download/upload of the at least one file.

A firmware update method and apparatus of a set-top box for a digital broadcast system is provided. A firmware update method of a set-top box for a digital broadcast system includes determining whether a newly received Code Version Table (CVT) following a public CVT which has been previously received and stored is the public CVT or a filtering CVT; and updating, when the newly received CVG is the filtering CVT, the firmware of the set-top box with a filtering firmware indicated by the filtering CVT.

Apparatus and method for assessing odors, comprises an electronic nose, to be applied to an odor and to output a structure identifying the odor; a neural network which maps an extracted structure to a first location on a pre-learned axis of odor pleasantness; and an output for outputting an assessment of an applied odor based on said first location. The assessment may be a prediction of how pleasant a user will consider the odor.