Panel fasteners, panel assemblies, methods of assembly and installation of panel assemblies and panel fasteners, anchor systems, anchor systems with captive fasteners and assemblies are disclosed.

Decorative toilet bolt caps having and elongated tube positioned above an aperture are disclosed. The cap may be formed of a single unit of material. By virtue of having an elongated tube positioned above an aperture, the cap may cover a closet bolt having an unreduced length.

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A digitally controlled oscillator has a high-order ΔΣ modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ΔΣ modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision.

The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.

Embodiments of the present invention provide a temperature compensation method and a crystal oscillator, where the crystal oscillator includes a crystal oscillation circuit unit, a temperature sensor unit, an oscillation controlling unit, a relative temperature calculating unit, and a temperature compensating unit. The temperature sensor unit measures a measured temperature of the crystal oscillation circuit unit; the relative temperature calculating unit obtains a temperature difference between the measured temperature and a reference temperature; the temperature compensating unit obtains a temperature compensation value corresponding to the temperature difference from a temperature-frequency curve; and the oscillation controlling unit generates a frequency control signal, according to a frequency tracked by a communications AFC device and the temperature compensation value, thereby controlling a frequency of the crystal oscillation circuit unit to work on the tracked frequency.

Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal.

A crystal controlled oscillator includes a crystal package and an IC chip board that includes an IC chip integrating an oscillator circuit. The crystal package includes a first container, a crystal resonator, a lid body, and an external terminal at an outer bottom surface of the first bottom wall layer of the first container. The IC chip integrates an oscillator circuit disposed at an outer bottom surface of the first bottom wall layer of the crystal package. The oscillator circuit connects to the lower side excitation electrode of the crystal resonator from the external terminal to an input side with high impedance. The oscillator circuit connects to the upper side excitation electrode to an output side with low impedance. The upper side excitation electrode is a shielding electrode of the crystal resonator.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

A protective film to a polarizer including a cellulose acylate and satisfying the following requirement (1) or (2): (1): The surface of the film has a pH of from 3.0 to 4.5.(2): The surface of the film has a pH of more than 4.5 and at most 6.0, and the film has a moisture permeability of at least 2800 g/m2·day.

Provided is a switching liquid crystal panel and a display device that have novel structures that are capable of preventing luminous regions from appearing in the light transmitting parts, in the vicinities of boundaries thereof with the light shielding parts. The switching liquid crystal panel includes a pair of substrates (26a, 26b) having a twisted nematic type liquid crystal layer (24) interposed therebetween, and a plurality of light shield forming electrodes (30) that are formed on at least one of the pair of the substrates (26a, 26b) and that form light shielding parts (40) of a parallax barrier (16) in cooperation with a counter electrode (34) when a voltage is applied, the counter electrode (34) being is opposed to the light shield forming electrodes (30) with the liquid crystal layer (24) interposed therebetween. A rubbing direction for an alignment film (36a) provided on the substrate (26a) side on which the light shield forming electrodes (30) are formed is at an angle of 45° or less to a lengthwise direction of the light shield forming electrodes (30).

A liquid crystal display element disclosed includes: a first substrate; a second substrate; a liquid crystal layer sandwiched between the first substrate and the second substrate; a first transparent electrode provided at a display region of the first substrate; and a second transparent electrode provided at a display region of the second substrate, at least one of d1 and d2 being not larger than 60 nm, where d1 represents a thickness of the first transparent electrode and d2 represents a thickness of the second transparent electrode.

Provided is a liquid crystal display including, on an insulation substrate having a polygonal display area and a peripheral area surrounding the display area a first signal line, a second signal line crossing the first signal line, a plurality of switching elements connected to the first signal line and the second signal line and disposed in the display area, a plurality of pixel electrodes each connected to the switching element and disposed in the display area, and a shielding conductor disposed in the peripheral area and extending along at least one side of the polygonal display area.

Provided is a back plate component having reflective sheet reinforcing structure. The back plate component includes: a frame, a reflective sheet and a plurality of supporting film sheets. The frame includes a plurality of lateral beams and vertical beams, and at least one hollow part is included between the lateral beams and the vertical beams. The reflective sheet is attached to the frame, and includes a reflective surface and a back surface corresponding to the reflective surface. A portion of the back surface covers the whole hollow part. The plurality of supporting film sheets is attached to the back surface at a region corresponding to the hollow part, and includes a material the same as that of the reflective sheet. A liquid crystal display device is further disclosed herein.

A liquid crystal display device includes a first substrate, a first electrode on the first substrate, a second substrate opposed to the first substrate, and a second electrode on the second substrate. The second electrode corresponds to the first electrode. The liquid crystal display device also includes a liquid crystal structure between the first electrode and the second electrode. The liquid crystal structure includes a plurality of liquid crystal molecules and at least one movement control member. The movement control member in the liquid crystal structure restricts a movement of the liquid crystal molecules.

The present invention provides an optical compensated bending (OCB) mode liquid crystal display (LCD) panel and a method for manufacturing the same. The method comprises the following steps: forming alignment layers on substrate, respectively; forming a liquid crystal layer between the alignment layers to form a liquid crystal cell; applying an electrical signal across the liquid crystal cell; and irradiating light rays to or heating the liquid crystal cell, so as to form a first polymer alignment layer and a second polymer alignment layer, respectively. The present invention can reduce a phase transition time of liquid crystal molecules from a splay state to a bent state.

A liquid crystal display being capable of improving the contrast ratio in the front direction thereof is provided. A liquid crystal display 100 of the present invention includes, in sequence: a light source device 14 that emits a parallel light beam; a back surface-side polarizer 16; a liquid crystal cell 13; a display surface-side polarizer 11; and a light diffusion layer 15. The liquid crystal display 100 further includes: a selective light-shielding layer 12 between the display surface-side polarizer 11 and the light diffusion layer 15 so that the selective light-shielding layer 12 shields light that is generated by being depolarized and scattered in the liquid crystal cell 13 and travels in a direction that is different from a direction in which the parallel light beam travels.

There is provided an optical laminate which comprises: a polarizing film wherein a thin polarizing layer is laminated on one main surface of a substrate; and an optical element (lens array). The thin polarizing layer has a thickness of 8 μm or less. The substrate has a thickness of 20 μm to 80 μm. The optical element is a pattern retardation plate including a plurality of regions having different slow axis directions.

A counter substrate for liquid crystal display includes a transparent substrate, a black matrix, and stripe transparent electrodes. The black matrix divides a plane surface of the transparent substrate into pixel or sub-pixel unit to form a light-shielded area and openings above the plane surface. The stripe transparent electrodes are formed into the pixel unit or the sub-pixel unit above the plane surface. The black matrix includes a frame pattern including two sides facing each other in parallel in the pixel or the sub-pixel unit, and a linear central pattern which is parallel to the two sides of the frame pattern and is formed at a midsection of the pixel or the sub-pixel unit. The transparent electrodes are each parallel to the two sides of the frame pattern and the central pattern and are located symmetrically to the central pattern.

A transverse electric field type liquid crystal display panel includes a pair of substrates opposed with a liquid crystal layer interposed therebetween. A plurality of sub-pixels having at least one curved portion in a display area are provided in a matrix on one side of the pair of substrates, and a pair of electrodes having at least one curved portion are formed in the plurality of sub-pixels. A light shield layer shielding a non-display area positioned on an outer peripheral side of the display area and between the plurality of sub-pixels is formed on the other side of the pair of substrates. The light shield layer of the non-display area is formed in a shape in which the outermost peripheral side of the display area is rectangular.

Disclosed herein is a liquid crystal display device including a plurality of pixels each having a reflecting section and a transmitting section, the pixels each including a plurality of sub-pixels resulting from alignment division, the liquid crystal display device including: an element layer formed on a substrate; an insulating film formed on the substrate so as to cover the element layer; a pixel electrode formed on the insulating film so as to be connected to the element layer; a gap adjusting layer formed on the insulating film on the element layer including a region of connection between the element layer and the pixel electrode; and a dielectric formed on a connecting part for making an electric connection between the sub-pixels.

A liquid crystal display device includes a liquid crystal display element including a first alignment film and a second alignment film and a liquid crystal layer that is provided between the first alignment film and the second alignment film, wherein the first alignment film includes a compound in which a polymer compound that includes a cross-linked functional group or a polymerized functional group as a side chain is cross-linked or polymerized, the second alignment film includes the same compound as the compound that configures the first alignment film, and the formation and processing of the second alignment film is different from the formation and processing of the first alignment film and when a pretilt angle of the liquid crystal molecules which is conferred by the first alignment film is θ1 and a pretilt angle of the liquid crystal molecules which is conferred by the second alignment film is θ2, θ1>θ2.

The present invention provides a display device substrate, a display device substrate manufacturing method, a display device, a liquid crystal display device, a liquid crystal display device manufacturing method and an organic electroluminescent display device that allow suppressing faults derived from occurrence of gas and/or bubbles in a pixel region. The present invention is a display device substrate that comprises: a photosensitive resin film; and a pixel electrode, in this order, from a side of an insulating substrate. The display device substrate has a gas-barrier insulating film, at a layer higher than the photosensitive resin film, for preventing advance of a gas generated from the photosensitive resin film, or has a gas-barrier insulating film, between the photosensitive resin film and the pixel electrode, for preventing advance of gas generated from the photosensitive resin film.

The disclosed technology discloses an array substrate and a liquid crystal display panel. The array substrate comprises: a base substrate; a gate line and a data line formed on the base substrate, the gate line and the data line defining a plurality of pixel regions; and a first electrode layer and a second electrode layer formed in each pixel region; and an insulating layer provided between the first electrode layer and the second electrode layer. The first electrode layer, the insulating layer and the second electrode layer are laminated on the base substrate in this order. The first electrode layer is provided with a plurality of first apertures therein, and the first electrode layer comprises a plurality of first electrode portions located between the plurality of first apertures.

A pixel structure comprises a plurality of pixel regions, and each of the pixel regions includes first and second electrodes that are overlapped with each other, the first electrode is disposed above the second electrode, and each of the pixel regions is divided at least into a first to fourth domain display regions; strip-shaped first electrodes in the first to fourth domain display regions make first to fourth angles with a reference direction; the sum of the first angle and the second angle is 180 degrees, the sum of the third angle and the fourth angle is 180 degrees, and the first, the second, the third and the fourth angles are different from one another.

Apertures are formed in the common electrode or in the pixel electrode of a liquid crystal display to form a fringe field. Storage capacitor electrodes are formed at the position corresponding to the apertures to prevent the light leakage due to the disclination caused by the fringe field. The apertures extend horizontally, vertically or obliquely. The apertures in adjacent pixel regions may have different directions to widen the viewing angle.

The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

A liquid crystal display device includes a TFT substrate having a display region with first and second electrodes, TFTs, scanning signal lines connected to the TFTs, a counter substrate, a liquid crystal layer sandwiched between the TFT and counter substrates, and sealed by a sealant, scanning line leads connected to the scanning signal lines and formed outside of the display region, video signal line leads connected to the video signal lines and formed outside of the display region and a shield electrode formed on the TFT substrate covering the scanning line leads but not the video signal line leads. The second electrode is connected to one of the TFTs, and liquid crystal molecules of the liquid crystal layer are driven by an electric field, which is generated between the first and second electrodes. The shield electrode is electrically connected to the first electrode and overlapped with the sealant in plan view.

One of the objects of the present invention is to provide a liquid crystal display device with high transmittance or viewing angle characteristics. A liquid crystal display device of the present invention includes: a first substrate (10) which includes a pixel electrode (30); a second substrate (20) which includes a counter electrode (25); and a liquid crystal layer (21) and a spacer (40) which are provided between the first substrate (10) and the second substrate (20). The pixel electrode (30) includes a first portion which is formed by a plurality of first branch portions (34A) extending in a first direction, a second portion which is formed by a plurality of second branch portions (34B) extending in a second direction, a third portion which is formed by a plurality of third branch portions (34C) extending in a third direction, and a fourth portion which is formed by a plurality of fourth branch portions (34D) extending in a fourth direction. The spacer (40) is provided at a position in the pixel (50) which is surrounded by the first to fourth portions of the pixel electrode (30) when viewed from a direction perpendicular to a plane of the first substrate (10).

In a conventional bistable liquid crystal device, switching characteristics fluctuate among panels and there is a problem in mass productivity. As an intermediate layer, an uneven film is inserted between a low anchoring layer and ITO. The uneven film has an average surface roughness of 2 nm or less, which is measured by an atomic force microscope. In this manner, the low anchoring layer is not affected by the surface shape of the ITO film which differs among panels, and the switching characteristics are stabilized.

An optical switch for performing high extinction ratio switching of an optical signal includes a beam polarizing element and one or more optical elements. The optical elements are configured to direct an optical signal along a first or second optical path based on the polarization state of the optical signal as it passes through the optical elements. The optical switch performs high extinction ratio switching of the optical signal by preventing unwanted optical energy from entering an output port by using an absorptive or reflective optical element or by directing the unwanted optical energy along a different optical path.

A liquid crystal display panel, including: a pixel electrode formed on a first substrate; an alignment layer formed on the pixel electrode, wherein the alignment layer includes an alignment layer material and aligns first liquid crystal molecules in a direction substantially perpendicular to the pixel electrode; and a photo hardening layer formed on the alignment layer, wherein the photo hardening layer includes a photo hardening layer material and aligns second liquid crystal molecules to be tilted with respect to the pixel electrode, wherein the alignment layer material and the photo hardening layer material have different polarities from each other.

It is an object of the present invention to provide a liquid crystal display device which has a wide viewing angle and less color-shift depending on an angle at which a display screen is seen and can display an image favorably recognized both outdoors in sunlight and dark indoors (or outdoors at night). The liquid crystal display device includes a first portion where display is performed by transmission of light and a second portion where display is performed by reflection of light. Further, a liquid crystal layer includes a liquid crystal molecule which rotates parallel to an electrode plane when a potential difference is generated between two electrodes of a liquid crystal element provided below the liquid crystal layer.

A liquid crystal display capable of realizing a high transmittance while maintaining favorable voltage response characteristics, and a method of manufacturing the same are provided. The liquid crystal display includes: a liquid crystal layer; a first substrate and a second substrate arranged to face each other with the liquid crystal layer in between; a plurality of pixel electrodes provided on a liquid crystal layer side of the first substrate; and an opposite electrode provided on the second substrate to face the plurality of pixel electrodes. One or both of a face on the liquid crystal layer side of the pixel electrode, and a face on the liquid crystal layer side of the opposite electrode includes a concavo-convex structure.

The present invention provides a backlight module and a liquid crystal display device using the backlight module. The backlight module includes: a backplane (2), a light guide plate (4) arranged in the backplane (2), a backlight source (6) arranged in the backplane (2), an optic film assembly (8) arranged above the light guide plate (4), and a reflection plate (9) arranged between the backplane (2) and the light guide plate (4). The backlight source (6) includes a PCB (62) and a plurality of LED lights (64) mounted on and electrically connected to the PCB (62). The backplane (2) includes a bottom plate (22) and a plurality of side plates (24) perpendicularly connected to the bottom plate (22). The bottom plate (22) of the backplane (2) includes a snap-engagement structure (220) formed thereon. The PCB (62) is snap-fit into and retained by the snap-engagement structure (220). The reflection plate (9) is directly positioned on and supported by the PCB (62).