A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating.

The invention provides a method and apparatus for creating plasma particles and applying the plasma particles to a liquid. Liquid feedstock (e.g., water and/or hydrocarbons mixed with biomass) is pumped through a pipeline; the single-phase stream is then transformed into a biphasic liquid-and-gas stream inside a chamber. The transformation is achieved by transitioning the stream from a high pressure zone to a lower-pressure zone. The pressure drop may occur when the stream further passes through a device for atomizing liquid. Inside the chamber, an electric field is generated with an intensity level that exceeds the threshold of breakdown voltage of the biphasic medium leading to a generation of a plasma state. Furthermore, the invention provides an energy-efficient highly adaptable and versatile method and apparatus for sanitizing water using plasma particles to inactivate biological agents contaminating water.

The cost relating to a reduction in volume and storage of a waste resin including a radioactive nuclide is reduced. In an aspect of the invention, a volume reduction processing system 1000 is provided. The volume reduction processing system 1000 includes a radioactivity meter 102 that measures the radioactivity of a processing target resin, a volume reduction processing device 110 that carries out a heating process, and an oxidation process using oxygen plasma P on the processing target resin, and a process stopping point computation unit 180 that determines a process stopping point for carrying out a volume reduction process on the processing target resin with the volume reduction processing device as far as a volume reduction target value. The volume reduction processing device 110 stops at least one process of the heating process and oxidation process on the process stopping point being reached.

A method and device for limiting the degassing of tritiated waste issued from the nuclear industry are provided. The method reduces an amount of generated tritiated hydrogen (T2 or HT) and/or tritiated water (HTO or T2O) including at least one piece of tritiated waste from the nuclear industry. The method includes placing the package in contact with a mixture including manganese dioxide (MnO2) combined with a component that includes silver; and placing the package in contact with a molecular sieve.

A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals. The second permutation device performs a one-dimensional order permutation operation for generating N one-dimensional output signals. The N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator.

Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

The present invention provides a polymerization reactor for producing a super absorbent polymer comprising: a reaction unit; a monomer composition supply unit being connected to the reaction unit and supplying a monomer composition solution containing a monomer, a photoinitiator, and a solvent; an agitating shaft extended in the reaction unit from one end of the reaction unit connected to the monomer composition supply unit to the other end of the reaction unit; a plurality of agitating blades installed around the agitating shaft; and a light irradiation unit providing light to the monomer composition solution furnished from the monomer composition supply unit, and a method of producing super absorbent polymers by using the same.

Disclosed is a resin precursor composition including a bifunctional (meth)acrylate containing a fluorine atom, a bifunctional (meth)acrylate having a fluorene structure, and a photopolymerization initiator, the resin precursor composition in which the formation of precipitates during its storage is suppressed; and a resin obtained from the same. Specifically disclosed is a resin precursor composition that contains a bifunctional fluorine-containing (meth)acrylate (component A); a (meth)acrylate having a fluorene structure (component B); and a photopolymerization initiator (component C), wherein the component B includes a bifunctional (meth)acrylate having a fluorene structure (b-1) and a monofunctional (meth)acrylate having a fluorene structure (b-2) at a molar ratio (b-1):(b-2) of 90:10 to 70:30.

Described is a radiation-crosslinkable hotmelt adhesive comprising at least one radiation-crosslinkable poly(meth)acrylate formed to an extent of at least 60% by weight of C1 to C10 alkyl(meth)acrylates and at least one oligo(meth)acrylate which comprises nonacrylic C C double bonds and has a K value of less than or equal to 20. The hotmelt adhesive comprises a photoinitiator which may be present in the form of an additive not attached to the poly(meth)acrylate and/or not attached to the oligo(meth)acrylate, may be incorporated by copolymerization into the poly(meth)acrylate, and/or may be attached to the oligo(meth)acrylate. The hotmelt adhesive can be used for producing adhesive tapes.

A durable ambient light curable waterproof liquid rubber coating with volatile organic compound (VOC) content of less than 450 grams per liter made from ethylene propylene diene terpolymer (EPDM) in a solvent, a photoinitiator, an additive, pigments, and fillers, and a co-agent and a method for making the formulation, wherein the formulation is devoid of thermally activated accelerators.

The present disclosure relates to a thermally resistant optical siloxane resin composition including siloxane containing photo-cationically polymerizable epoxy group, a photo initiator, and an antioxidant.

A photocurable material for sealing including (A) an oligomer having a weight average molecular weight of 10,000 to 30,000 and having (meth)acryloyl group(s), (B) a (meth)acrylate monomer, (C) a polythiol compound, and optionally (D) a carbodiimide compound enables the provision of a sealing material that has high compression recovery performance, high tensile strength and excellent flexibility, can have low hardness if required, and therefore has excellent sealing properties including air-tightness performance and water-proof performance and undergoes the formation of little surface tacks and the like.

A heat-resistant cured product is efficiently produced by obtaining a semi-cured product where a curable resin composition containing a (meth)acrylate monomer, a non-conjugated vinylidene group-containing compound and a thermal radical-polymerization initiator is processed by at least one of photoirradiation and heating to give a semi-cured product having a complex viscosity of from 105 to 108 mPa·s at 25° C. and at a frequency of 10 Hz; and putting the semi-cured product in a forming die for pressure formation therein, and heating it therein for thermal polymerization to give a cured product.

A method includes configuring a processing circuit to perform: receiving a control word for an I/O operation, forwarding a transport command control block (TCCB) from the channel subsystem to a control unit, gathering data associated with the I/O operation, and transmitting the gathered data to the control unit in the I/O processing system. Gathering the data includes accessing entries of a list of storage addresses that collectively specifying the data. Based on an entry of the list comprising a not-set first flag and a corresponding first storage address, gathering data from a corresponding storage location, and based on an entry of the list comprising a set first flag and a corresponding second storage address, obtaining a next entry of the list from a second storage location.

Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate. A transfer rate at which the storage device transfers data is set to the selected recording medium transfer rate.

An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element can be freed.

An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device (30) includes a processor core (301); coprocessors (311 to 31n) including operation units (321 to 32n) that perform operation in response to a request from the processor core (301) and operation storage units (331 to 22n) that store the contents of operation of the operation units (321 to 32n), save storage units (351 to 35n) that store the saved contents of operation, a task switching control unit (302) that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors (311 to 31n), and save/restore units (341 to 34n) that perform at least one of saving of the contents of operation in the operation storage units (331 to 33n) to the save storage units (351 to 35n) and restoration of the contents of operation in the save storage units (351 to 35 n) to the operation storage units (331 to 33n) in response to the save/restore request signal.

The present invention provides a method for separating halocarbons. In particular, the invention provides a method for separating halogenated olefin impurities from 2-chloro-1,1,1,2-tetrafluoropropane (HCFC-244bb) using a solid adsorbent, particularly activated carbon. More particularly the invention pertains to a method for separating 2-chloro-3,3,3-trifluoro-propene (HCFO-1233xf) from HCFC-244bb, which are useful as intermediates in the production of 2,3,3,3-tetrafluoropropene (HFO-1234yf).

Process for producing silica-comprising dispersions comprising a polyetherol or a polyether amine, which comprises the steps of (i) admixing an aqueous silica sol (K) having an average particle diameter of from 1 to 150 nm and a silica content, calculated as SiO2, of from 1 to 60% by weight and a pH of from 1 to 6 with at least one polyetherol (b1) and/or polyether amine (b2) based on ethylene oxide and/or propylene oxide and having an average OH or amine functionality of from 2 to 6 and a number average molecular weight of from 62 to 6000 g/mol,(ii) distilling off at least part of the water,(iii) admixing the dispersion with at least one compound (S) having at least one at least monoalkoxylated silyl group and at least one alkyl, cycloalkyl or aryl substituent, where this substituent may have groups which are reactive toward an alcohol, an amine or an isocyanate in an amount of from 0.1 to 20 μmol of (S) per m2 of surface area of (K), where steps (i) and (iii) can be carried out simultaneously or in succession in any order, (iv) optionally adjusting the pH of the silica-comprising dispersions obtained to a value of from 7 to 12 by adding a basic compound, where step (iv) can also be carried out between steps (ii) and (iii).

Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the complex in supercritical carbon dioxide. The Lewis acid is soluble in supercritical carbon dioxide, and the base is substantially insoluble in supercritical carbon dioxide. Methods for increasing the solubility of water in supercritical carbon dioxide include dissolving an acid or a base in supercritical carbon dioxide to form a solution and dissolving water in the solution. The acid or the base is formulated to interact with water to solubilize the water in the supercritical carbon dioxide. Some compositions include supercritical carbon dioxide, a hydrolysable metallic compound, and at least one of an acid and a base. Some compositions include an alkoxide and at least one of an acid and a base.

The present invention relates to compositions for use in refrigeration, air-conditioning, and heat pump systems wherein the composition comprises E-1,2-difluoroethylene. The compositions of the present invention are useful in processes for producing cooling or heat, as heat transfer fluids, foam blowing agents, aerosol propellants, and power cycle working fluids.

The present invention relates to compositions for use in refrigeration, air-conditioning, and heat pump systems wherein the composition comprises Z-1,2-difluoroethylene (Z-HFO-1132a). The compositions of the present invention are useful in processes for producing cooling or heat, as heat transfer fluids, foam blowing agents, aerosol propellants, and power cycle working fluids.

Particular aspects provide compositions comprising an electrokinetically altered oxygenated aqueous fluid, wherein the oxygen in the fluid is present in an amount of at least 25 ppm. In certain aspects, the electrokinetically altered oxygenated aqueous fluid comprises electrokinetically modified or charged oxygen species present in an amount of at least 0.5 ppm. In certain aspects the electrokinetically altered oxygenated aqueous fluid comprises solvated electrons stabilized by molecular oxygen, and wherein the solvated electrons present in an amount of at least 0.01 ppm. In certain aspects, the fluid facilitates oxidation of pyrogallol to purpurogallin in the presence of horseradish peroxidase enzyme (HRP) in an amount above that afforded by a control pressure pot generated or fine-bubble generated aqueous fluid having an equivalent dissolved oxygen level, and wherein there is no hydrogen peroxide, or less than 0.1 ppm of hydrogen peroxide present in the electrokinetic oxygen-enriched aqueous fluid.

The disclosure relates to methods of making polymer particles, said methods including the steps of: making an aqueous gel reaction mixture; forming an emulsion having dispersed aqueous phase micelles of gel reaction mixture in a continuous phase; adding an initiator oil comprising at least one polymerization initiator to the continuous phase; and performing a polymerization reaction in the micelles. Further, the initiator oil is present in a volume % relative to a volume of the aqueous gel reaction mixture of between about 1 vol % to about 20 vol %. The disclosure also relates to methods of making nucleic acid polymer particles having the same method steps and wherein the aqueous gel reaction mixture includes a nucleic acid fragment, such as a primer.

A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.

A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.

A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.