A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

An apparatus for assigning a plurality of access nodes of a wireless communication network to control areas includes a processing apparatus. The processing apparatus is configured to assign each access node in the plurality of access nodes to a control area of a plurality of control areas and to determine a first control phase. The first control phase is a period of time during which the assignment of access nodes to control areas remains constant. The processing apparatus is configured to, when changing from the first control phase to a following second control phase, reassign at least a subset of access nodes which were assigned during the first control phase to a first control area to a second control area and reassign at least a subset of access nodes which were assigned during the first control phase to a third control area to the first control area.

A method for transmitting uplink (UL) data requiring low latency in a wireless communication system according to the present invention, the method performed by a user equipment comprises transmitting contention PUSCH resource block (CPRB) indication information used for identifying a particular UE and/or particular data to an eNB; transmitting UL data to the eNB through CPRB resources of a contention based PUSCH (CP) zone; and receiving a hybrid automatic retransmit request (HARQ) response with respect to the UL data from the eNB through a physical hybrid ARQ indicator channel (PHICH).

Methods and apparatus for multiple user uplink are provided. In one aspect, method for wireless communication includes receiving an assignment of a frequency bandwidth for an uplink transmission of a station. The method further includes determining whether a portion of the assigned frequency bandwidth is unavailable for the uplink transmission. The method further includes selectively transmitting the uplink transmission based on whether the portion of the assigned frequency bandwidth is unavailable.

A first communication device and method therein for transmitting data information at fixed time instants on a radio channel to a second communication device in a radio communications network. First, the first communication device determines that the radio channel is available for transmitting data information to the second communication device during a time period determined by the first communication device. Then, the first communication device transmits a preamble on the available radio channel after the time period. The first communication device thereafter transmits the data information on the available radio channel to the second communication device at a next fixed time instant following the transmission of the preamble.

A data transmission apparatus in a communication system includes a reception unit configured to receive terminal information from a plurality of terminals through a new frequency band for transmission and reception of data between the plurality of terminals and an AP (access point); a determination unit configured to determine access timing of the terminals to the AP by using the terminal information, and generate terminal access information including information on the access timing; and a transmission unit configured to transmit the terminal access information and beacon frames to the terminals, wherein the terminals access the AP and transmit data frames to the AP, at the access timing based on the beacon frames.

Disclosed are a method for transmitting and receiving a frame in a wireless local area network (WLAN) system and an apparatus for the same. A method for generating interference/non-interference station lists includes receiving a first frame from a second station, acquiring a receiver address of the first frame from the first frame, and setting, based on whether to receive a second frame that is a response to the first frame from a third station indicated by the receiver address within a preset time from a time when the first frame has been received, the third station as an interference station or a non-interference station. Therefore, the performance of a communication system may be improved.

This disclosure describes methods, devices, and systems related to an OFDMA Distributed Channel Access. Devices are disclosed comprising: at least one processor; and at least one memory that stores computer-executable instructions, wherein the at least one processor is configured to access the at least one memory and execute the computer-executable instructions to identify a trigger frame received on the communication channel from the computing device. The at least one processor may determine an uplink frame to be sent to a computing device on a communication channel. The at least one processor may identify one or more random access resource allocations, wherein the one or more random access resource allocations are associated with the trigger frame. The at least one processor may assign a respective numerical value to each of the one or more random access resource allocations. The at least one processor may also select a numerical value based at least in part on a probability distribution. The at least one processor may also determine a particular resource allocation of the one or more random access resource allocations that corresponds to the numerical value. The at least one processor may also cause the uplink frame to be sent to the computing device using the particular resource allocation.

Disclosed are a method and an apparatus for generating a codeword, and a method and an apparatus for recovering a codeword. An encoder calculates the number of punctured symbol nodes among symbol nodes included in a codeword, punctures symbol nodes located at even or odd number positions among the symbol nodes included in the codeword, calculates the number of symbol nodes which need to be additionally punctured on the basis of the calculated number of the symbol nodes to be punctured, classifies the symbol nodes, which need to be additionally punctured, into one or more punctured node groups on the basis of the calculated number of symbol nodes which need to be punctured, determines the locations on the codeword where the one or more punctured node groups are to be arranged, and punctures the symbol nodes included in the codeword which belong to the punctured node groups according to the determined locations. A transmission unit transmits the codeword.

Methods, apparatuses, computer readable media for spatial reuse for uplink multi-user transmissions. An apparatus of a station comprising processing circuitry is disclosed. The processing circuitry may be configured to decode a first portion of a physical layer convergence procedure (PLCP) protocol data unit (PPDU), and configure the station to transmit a frame, if the PPDU is an overlapping basic service set (OBSS) PPDU, and a receive power of the PPDU is below an overlapping power detect level. An apparatus of an access point comprising processing circuitry is disclosed. The processing circuitry may be configured to encode a PPDU comprising a basic service set identifier of the access point, and encode the PPDU to indicate spatial reuse (SR) delay, SR restricted, or SR not permitted. The processing circuitry may be further configured to configure the access point to transmit the PPDU.

An apparatus, system and method are provided for transmitting data from logical channel queues over a telecommunications link, each of the logical channel queues capable of being associated with quality of service attributes, the method including determining available resources for transmission over the telecommunications link in a frame; selecting one of the logical channel queues based on a first one of the quality of service attributes; packaging data from the selected one of the logical channel queues until one of: a second one of the quality of service attributes for the selected one of the logical channel queues is satisfied, the available resources are used, or the selected one of the logical channel queues is empty; and repeating the selecting step and the packaging step for remaining ones of the logical channel queues.

A technology is disclosed for an evolved Node B (eNB). The eNB can determine a set of configuration indication fields numbered 1 to N, included in a downlink control information (DCI) format Y carried on the PDCCH, where N=⌊LformatYM⌋, Lformat Y is equal to a payload size of the DCI format Y, and M is a number of bits of each indication field. The eNB can map the DCI format Y onto the PDCCH. The eNB can encode for transmission from to the UE the PDCCH with a cyclic redundancy check (CRC) scrambled by an enhanced interference mitigation and traffic adaptation (eIMTA) Radio-Network Temporary Identifier (RNTI) for the UE.

A system that incorporates the subject disclosure may perform, for example, a method for detecting signal interference in a first segment of a plurality of segments of a radio frequency spectrum of a wireless communication system, determining according to the signal interference a measure of quality of service of the first segment for transmitting voice traffic, comparing the measure of quality of service to a desired measure of quality of service measure for voice traffic, determining from the comparison that the first segment is not suitable for voice traffic, and notifying a system that the first segment is not suitable for voice traffic. Other embodiments are disclosed.

The present invention relates to a wireless communication system, and a method for determining a resource for device-to-device communication by a user equipment is disclosed. A method for determining a resource for device-to-device communication according to an embodiment of the present invention may comprise the steps of: receiving, from an eNode B (eNB), configuration information related to a resource pool configured for each level; selecting the resource pool of the device-to-device communication on the basis of the configuration information; and selecting a resource for the device-to-device communication in the resource pool. Herein, the resource pool may be configured to have two or more levels.

A first wireless device may determine a bandwidth for transmitting a frame, calculate two or more Spatial Reuse (SR) parameter values for the bandwidth, set, using the SR parameter values, first and second SR fields of the frame based on the bandwidth and a channel center frequency in which the bandwidth is carried, and transmit the frame to a second wireless device on the bandwidth. The first and second SR fields may be set to a first value when the bandwidth is a 40 MHz bandwidth and the channel center frequency is in a 2.4 GHz band. The first and second SR fields may be set to the first value when the bandwidth is an 80+80 MHz bandwidth and the channel center frequency is in a 5 GHz band. The first value may be a minimum of SR parameter values for first and second bandwidths in the bandwidth.

In one embodiment, a device of a first wireless communication network determines a link budget from a terminal in the first communication network to an unintended receiver for a communication from the terminal to an intended receiver in the first wireless communication network, based on the communication being configured with initial communication parameters. The device also determines whether one or more adjusted communication parameters would result in reducing a received power at the unintended receiver being below a link budget threshold, while still satisfying a receive sensitivity of the intended receiver. If so, the device causes the terminal to transmit the communication using the adjusted communication parameters. In one embodiment, the device is the terminal, and causing comprises transmitting as the terminal. In another embodiment, the device is a server of the first communication network, and causing comprises instructing the terminal to transmit the communication using the adjusted communication parameters.

A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

A method and a radio network node for scheduling wireless devices. The node assigns, to each wireless device, a D2D pair out of the D2D pairs based on spatial compatibilities for each of the D2D pairs with respect to each wireless device. The node estimates, for each wireless device and the assigned D2D pair, a first respective throughput for cellular communication and D2D communication, and estimates, for each wireless device, a second respective throughput for only cellular communication. The node schedules one or more of the wireless devices of the cellular network based on the first and second respective throughputs. Each of the wireless devices is scheduled for cellular communication together with the D2D communication of the assigned D2D pair when the first respective throughput exceeds the second respective throughput, or for only cellular communication when the first respective throughput is below the second respective throughput.

A wireless transmit/receive unit (WTRU) may receive a system information block (SIB) associated with proximity related localized applications broadcasted by an eNodeB. The WTRU may receive in response to sent location information, a proximity detection associated with another WTRU associated with the proximity related localized application. The transceiver may also receive scheduling information for a proximity related localized application and for other applications where a first radio network temporary identifier (RNTI) is for scheduling information for the proximity related localized application and a second RNTI is for scheduling information for the other applications.

A technique for emulating virtual port control of airtime fairness for wireless stations using per station Enhanced Distributed Channel Access (EDCA) parameters. Specific parameters are received for each of a plurality of stations connected to the access point. An EDCA field of a beacon that stores a general EDCA parameter is set to an empty state. The beacon is broadcast to a plurality stations on the wireless communication network and within range of an access point. The beacon comprises a BSSID (Basic Service Set Identifier) for use by the plurality of stations to connect with the access point for access to the wireless communication network. The beacon also comprises an empty EDCA field. In response to broadcasting the empty EDCA parameter, receiving a direct inquiry from each of the plurality of stations for the general EDCA parameter. Each of the plurality of stations is responded to with a direct communication of a specific parameter corresponding to each station. A transmission is received from at least one of the stations complying with the specific parameter.

A method, in a network node, for managing a wireless device is disclosed. The method comprises conducting spectrum opportunity detection within a spectrum band and indicating a result of the spectrum opportunity detection to the wireless device. For the purposes of the method, a spectrum opportunity comprises a channel within the spectrum band which is at least temporarily available for use by the wireless device. Also disclosed is a method in a wireless device in a network. The method comprises detecting an indication of a result of spectrum opportunity detection conducted by a network node within a spectrum band and if the indication indicates a detected spectrum opportunity, conducting one of a transmission or reception operation on the detected spectrum opportunity. Also disclosed are a computer program product for carrying out the above methods, a network node and a wireless device.

A method and network node for adaptation of contention windows in a multicarrier wireless communication system implementing a listen-before-talk protocol are disclosed. According to one aspect, a method includes determining at least one component carrier (CC), of multiple CCs to serve as a backoff channel. The method further includes performing a listen-before-talk procedure on the at least one CC serving as a backoff channel. The listen-before-talk procedure includes sensing for each backoff channel whether a clear channel exists during a backoff period drawn from a contention window (CW). The LBT procedure also includes deferring transmitting on a CC for which the sensing does not indicate that a clear channel exists. The LBT procedure also includes transmitting on a CC for which the sensing indicates a clear channel exists. The method also includes determining a size of the CW based on at least one transmission feedback value.

According to an aspect of the present invention, a device for communication according to a specific communication protocol is provided. The communication device includes a processor for generating and processing frames based on frame formats defined by the communication protocol. The processor generates a beacon frame so that information on a collision avoidance scheme supported by the device of a plurality kinds of information specified based on the communication protocol is omitted. Further, the processor processes a connection request frame transmitted from other device to extract information on a collision avoidance scheme supported by the other device, and controls communication with the other device based on comparison of the extracted information on the collision avoidance scheme with the information on the collision avoidance scheme supported by the device.

The sensing method a first vehicle user equipment (UE) for collision avoidance in a wireless communication network comprises receiving a set of scheduling assignment (SA) information allocated to a set of second vehicle UEs, decoding the set of SA information, each of which includes SA information to each of the set of second vehicle UEs, performing energy sensing operation for resources to be used by each of the set of second vehicle UEs to determine additional potential SA transmission and data transmission from the set of second vehicle UEs over the resources, determining available resources for the data transmission from the first vehicle UE based on the performed energy sensing and SA sensing, skipping a channel sensing operation on at least one subframe that is used for the data transmission from the first vehicle UE, and transmitting data among resources identified as unused in next transmissions from second vehicle UEs.