A boost converter with a multiple input and with improved efficiency has two or more inputs. A DC voltage source can be connected to each input. A common output carries a DC voltage whose value is greater than or equal to that of the input voltages. The common output is in each case connected to each of the plurality of inputs via a positive lead branch and a negative lead branch. At least one inductor is arranged in the positive lead branch and/or the negative lead branch from each input, and at least one rectification element is arranged in the positive lead branch and/or the negative lead branch from each input. Furthermore, the inputs can be connected in series by means of two or more switching elements via the inductors, wherein at least two of the inductors can in each case be connected in parallel.

An inverter circuit contains a first and second DC sources for providing a DC voltage, a common step-up converter for boosting the DC voltage, an intermediate circuit capacitor connected between the outputs of the common step-up converter, and an inverter for converting the DC voltage provided by the capacitor into an AC voltage. The common step-up converter contains a series circuit having a first inductance and a first rectifier element and is connected between an output of the first DC source and one side of the intermediate circuit capacitor as well as a series circuit which includes a second inductance and a second rectifier element and is connected between an output of the second DC source and another side of the intermediate circuit capacitor. The common step-up converter further contains a common switching element which is connected between the first and second DC sources.

A converter power unit comprises: a heat sink; n power switch modules on the heat sink; a first group of laminated bus bars comprising a first and a second bus bar; a capacitor group comprising m capacitor; a second group of laminated bus bars comprising a third and a fourth bus bar, the first bus bar is connected with the third bus bar, the second bus bar is connected with the fourth bus bar; providing that vertical projection areas projected by an area occupied by the n power switch modules and projected by the capacitor group on a first plane perpendicular to an axial direction of the capacitor group are defined as a first and a second projection areas respectively, the first and the second projection area have an overlapped area. The present application can reduce the stray inductances in the commutating loop of the converter.

The invention provides a laser converter for converting a laser radiation of shorter wavelength to a laser radiation of longer wavelength using a single stage conversion. The laser converter comprises a laser diode for emitting a laser radiation in a first wavelength range, a cylindrical microlens for transferring and focusing the laser radiation to a laser chip and the laser chip for absorbing the laser radiation and emitting the laser radiation in a second wavelength range.

A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code.

A power converter is configured to include an inverter which converts a DC output into an AC voltage of a predetermined frequency, and a high voltage generator which receives an output from output terminals of the inverter and boosts the output to a desired high DC voltage. The high voltage generator includes a transformer, and the primary windings of the transformer are connected to the output terminals of the inverter in parallel by conductive wires connected to both ends of each primary winding. Further, a current sensor is provided to detect a current flowing through each of the primary windings, and a control unit determines abnormalities of a path of the inverter and the primary windings on the basis of a value of the current sensor.

A generator system includes a generator having a stationary portion and a rotating portion. An exciter field winding and a main armature winding are disposed on the stationary portion. An exciter armature winding and a main field winding are disposed on the rotating portion. A frequency demodulator is configured to extract a frequency modulated control signal from the exciter armature winding and to demodulate the frequency modulated control signal to generate a demodulated control signal. The generator includes a main field rotating power converter to selectively control current in the main field winding in response to the demodulated command signal. The generator system includes a generator control unit in electrical communication with the generator to monitor the output voltage at the main armature winding and to output an exciter current including the frequency modulated control signal to the exciter field winding based on the output voltage.

A method of operating a converter of a wind turbine for providing electric energy to a utility grid includes determining a grid voltage. If the grid voltage is between a nominal voltage and a first voltage threshold, i.e. higher than the nominal voltage, a normal procedure for lowering the grid voltage is performed. If the grid voltage is above the first voltage threshold, another procedure for keeping the wind turbine connected is performed, wherein the other procedure is different from the normal procedure. Further a corresponding arrangement is described.

Systems and methods for reducing current imbalance between parallel bridge circuits used in a power converter of a doubly fed induction generator (DFIG) system are provided. A control system can monitor the bridge current of each of the bridge circuits coupled in parallel and generate a feedback signal indicative of the difference in bridge current between the parallel bridge circuits. Command signals for controlling the bridge circuits can then be developed based on the feedback signal to reduce current imbalance between the bridge circuits. For instance, the pulse width modulation of switching devices (e.g. IGBTs) used in the bridge circuits can be modified to reduce current imbalance between the parallel bridge circuits.

A double fed induction generator (DFIG) converter method are presented in which rotor side current spikes are attenuated using series-connected damping resistance in response to grid fault occurrences or grid fault clearances.

A DC voltage converter includes an oscillator that converts a DC battery voltage to an oscillating voltage, a low voltage transformer that increases the oscillating voltage to a higher oscillating voltage, and a voltage rectifying-capacitor charging network or multiplier that increases the higher oscillating voltage to yet a higher DC voltage at an output terminal for DC high voltage utilization devices and the like. An electric control switch is selectively actuated by the user to apply the battery voltage to the oscillator, resulting in the generation of the stepped-up DC voltage at an output terminal. Another DC voltage converter has an electronic switching circuit that automatically turns the oscillator on and off and a load capacitor across the electrodes that is charged and discharged to provide a shocking voltage. Utilization devices for the voltage developed by the converter shown are a miniature animal training device and a cattle prod device. The miniature animal training device has a pair of outwardly projecting electrodes mounted on a side at one end of the housing that is sized and shaped to fit within and conform to the palm of a hand. The cattle prod device has a pair of electrodes fixedly mounted on the end of a housing assembly made up of telescoping tubular housing sections arranged for relative axial movement whereby the pressing of the electrodes against an object to be shocked actuates the electric control switch and causes a shock of the object. The housing assembly is releasably supported by a rigid handle or an extensible handle assembly.

Provided is an A/D converter including an input terminal, a reference signal line for supplying a reference signal which changes temporally, a comparator, a correction capacitor connected to an inverting input terminal of the comparator; and an output circuit which outputs digital data corresponding to an analog signal input to the input terminal. In a first state in which a total voltage of a first analog signal and an offset voltage of the comparator is held in the correction capacitor, a second analog signal input to the input terminal is supplied to a non-inverting input terminal of the comparator, and the second analog signal or the total voltage is changed using the reference signal, thereby outputting, from the output circuit, digital data.

A power converter with positive and negative supply rail outputs for feeding a single ended class D amplifier, the converter comprising a transformer arrangement, a supply pump reduction arrangement connected between the secondary windings and the positive and negative supply rail outputs, and a boost drive mode switching arrangement. A controller is adapted to control the power converter in a negate drive mode and a boost drive mode, wherein the output voltage in the boost mode is increased by means of the transformer and the boost drive mode switching arrangement. The output voltages on the positive and negative rails can be generated at two different output voltage levels without changing the duty cycle or dead time of the control signals.

An apparatus is described that includes an audio power amplifier having an input and an output. An alternating-current to direct-current power converter is coupled to the audio power amplifier in a single package to supply power to the audio power amplifier.

A voltage converter can be switched among two or more modes to produce an output voltage tracking a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. One or more voltages generated from a power supply voltage, such as a battery voltage, can be compared with the reference voltage to determine whether to adjust the mode. The reference voltage can be independent of the power supply voltage.

The present invention is a serial to parallel data conversion method and device where new serial data are stored within a first n-bit register prior to presentation at an n-bit parallel output. Subsequently, additional data are stored within a second n-bit register while the data stored within the first register are presented at the parallel output. Data storage and data presentation are thereafter alternated, thereby eliminating the problem of setup time seen in prior art.

An analog-to-digital converter can use a variable sampling rate. By using a variable sampling rate analog-to-digital converter and an anti-aliasing filter lower sampling rates, and accordingly, generally lower power consumption may be achieved. For example, a lower sampling rate can be used when it is determined that no undesirable signals are present and a higher sampling period can be used when an undesirable signal is present. Determining the presence of an undesired signal can be based on signal-to-noise ratio, over-sampling, bit error rate, using a detector, etc. An undesirable signal can be any signal that is close in frequency to a signal of interest or a signal farther away in frequency that has a relatively high amplitude. Sampling rate can be varied in a binary fashion, stepwise, continuously, etc.

A DC-DC converter includes a first amplifier that amplifies a first difference between a first reference voltage and a feedback voltage corresponding to an output voltage, a second amplifier that amplifies a second difference between the first reference voltage and an integrated value of the feedback voltage, and a controller that controls a switching circuit to change the output voltage when the first difference reaches the second different.

A method of operating a switching power converter may include determining an average value of a measured parameter for substantially each switching cycle, and adjusting a control parameter during substantially each switching cycle in response to a corresponding one of the average values. In one embodiment, the control parameter comprises a switch duty cycle, and the measured parameter comprises an output current. Determining the average value of the measured parameter may include obtaining a first sample of the measured parameter during a switching cycle, and calculating the average value of the measured parameter during the switching cycle in response to the first sample.

Efficiency of a switch mode power supply (SMPS) is optimized by operating the SMPS in an asynchronous mode when current being supplied therefrom is less than a certain current value and operating the SMPS in a synchronous mode when the current being supplied therefrom is equal to or greater than the certain current value. When the SMPS is operating in the synchronous mode high-side and low-side power transistors alternately turn on and off. When the SMPS is operating in the asynchronous mode only the high-side power transistor turns on and off and the low-side power transistor remains off. When charging a battery with the SMPS discharge of the battery is eliminated when operating in the asynchronous mode at a low current output.

A power conversion system has a power converter configured to receive an input voltage signal, convert the input voltage to an output voltage signal, and provide the output voltage signal to a load and a closed loop compensator configured to receive the output voltage signal and a reference voltage signal, the closed loop compensator configured to transmit an error signal indicative of a difference between the output voltage signal and the reference voltage signal. The power conversion system further has a pulse with modulator configured to receive the error signal and modulate a control signal with the error signal to control the output voltage signal, the pulse width modulator configured to transmit the control signal to the power converter and logic configured to receive the error signal and control the closed loop compensator based upon the error signal. A controller observes the error signal characterstics such as peak-to-peak values, frequency and phase and adjust the closed loop controller variables and other power converter system variables in order to improve the dynamic performance and improve stability.

A DC/DC converter arrangement includes an input terminal to receive a supply voltage, an output terminal to provide an output voltage and a switching arrangement, including a coil and at least two switches to provide a Buck-Boost conversion. The arrangement further includes a current detection circuit which is coupled to the switching arrangement for sensing a coil current and a comparator, including a first input which is coupled to the output terminal and a second input which is coupled to an output of the current detection circuit. An output of the comparator is coupled to the switching arrangement. Furthermore, the arrangement includes a ramp generator which is coupled to the first or the second input of the comparator.

The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.

A controller used in a buck-boost converter includes a clock generator, an error amplifying circuit, a comparing circuit, a proportional sampling circuit, a logic circuit, a pulse width increasing circuit, first and second driving circuits. Based on a clock signal generated by the clock generator, the proportional sampling circuit samples the difference between a current sensing signal and a compensation signal generated by the error amplifying circuit, and generates a proportional sampling signal. The pulse width increasing circuit generates a sum control signal based on the proportional sampling signal and a logic control signal generated by the logic circuit, wherein a modulation value adjusted by the proportional sampling signal is added to the pulse width of the logic control signal to generate the pulse width of the sum control signal. The first and second driving circuits generate driving signals based on the sum control signal and the logic control signal.

A method for controlling voltage crossing a power switch of a switched-mode power converter includes the steps of: controlling a switch frequency of the power switch of the switched-mode power converter to a first frequency as activating the switched-mode power converter; and then changing the switch frequency of the power switch to a second frequency after the switched-mode power converter is activated for a predetermined time; wherein the first frequency is lower than the second frequency.

In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.

A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

A switching power converter includes a voltage source that provides an input voltage Vin to an unregulated DC/DC converter stage and at least one buck-boost converter stage to produce a desired output voltage Vout. The unregulated DC/DC converter stage is adapted to provide an isolated voltage to the at least one regulated buck-boost converter stage, wherein the unregulated DC/DC converter stage comprises a transformer having a primary winding and at least one secondary winding and at least one switching element coupled to the primary winding. The at least one buck-boost converter stage is arranged to operate in a buck mode, boost mode or buck-boost mode in response to a mode selection signal from a mode selection module. By influencing the pulse width modulation output power controller the at least one buck-boost converter stage is arranged to produce one or multiple output voltages.

A constant on-time switching converter includes a switching circuit, an on-time control circuit, a comparing circuit and a logic circuit. The switching circuit has a first switch and is configured to provide an output voltage to a load. The on-time control circuit generates an on-time control signal to control the on-time of the first switch. The comparing circuit compares the output voltage of the switching circuit with a reference signal and generates a comparison signal. The logic circuit generates a control signal to control the first switch based on the on-time control signal and the comparison signal. When the switching frequency of the switching circuit approaches an audible range, the switching converter enters into a sleep mode, the on-time control signal is reduced to increase the switching frequency of the switching circuit.

In various embodiments a controller for controlling the operation of a switched mode power supply is provided, the controller comprising: a first signal source configured to provide a first set of signals including a set signal and a clear signal, wherein the first set of signals may correspond to a first mode of operation of the switched mode power supply; a second signal source configured to provide a second set of signals including a set signal and a clear signal, wherein the second set of signals may correspond to a second mode of operation of the switched mode power supply; a selecting circuit coupled to the first signal source and to the second signal source, the selecting circuit being configured to select either the first set of signals or the second set of signals; a switching signal generating circuit coupled to the selecting circuit and configured to provide a switching signal to the switched mode power supply based on the set of signals received from the selecting circuit.

A synchronous DC-DC converter having a soft-stop function includes an output stage for supplying an output voltage, wherein the output stage includes a high-side transistor for charging the output voltage and a low-side transistor for discharging the output voltage; an output control circuit, coupled to the output stage, for controlling the high-side transistor and the low-side transistor of the output stage; at least one protection device, for controlling the high-side transistor to be turned off when a specific situation occurs, in order to stop supplying the output voltage; and a soft-stop control circuit, coupled to the output control circuit, for controlling the low-side transistor of the output stage to be turned on when the protection device controls the high-side transistor to be turned off or the synchronous DC-DC converter is disabled, in order to discharge the output voltage.

Polyphase converter, comprising a plurality of electrical phases (11 to 16), which can each be driven by switching means (21 to 26), wherein at least one coupling means (31 to 39) is provided, which magnetically couples at least one first phase (11) to at least one further phase (12, 14, 16), wherein at least two phases (11, 12) to be coupled are surrounded at least partially by the coupling means (31), wherein at least one insulating body (72) is provided, which on the upper or lower side thereof accommodates the phases (11 to 16) to be coupled and on which at least one fastening means (74, 76, 90) is provided, which interacts with at least one of the phases (11 to 16) for fastening purposes.

There is provided a DC-DC converter which converts an input voltage into an output voltage for supply to a load, in which an input terminal receives the input voltage, an output terminal outputs the output voltage, power stages each includes: a high side switch, a low side switch and an inductor, the control unit executes a first mode and a second mode wherein the first mode controls the high side switch and the low side switch in each of the power stages so that a ratio of an output current in each of the power stages to a load current flowing through the load becomes a set value and the second mode controls the high side switch and the low side switch in each of the power stages so that duty ratios of the high side switch and the low side switch are equalized among the power stages.

A muffler is capable of stably supporting the catalytic converter in a muffler box with a pair of partitions. The muffler box includes first and second box halves joined together with open surfaces thereof abutting each other, and first and second partition plates interposed between the first and second box halves and overlapping each other to separate inside of the muffler box into first and second silencing chambers and define a third silencing chamber between the first and second partition plates, one end opening of a cylindrical holding tube housing and holding the catalytic converter is connected to the exhaust inlet pipe, the pair of partition plates support the holding tube in such a way as to wrap an outer peripheral surface thereof, and another end opening of the holding tube is communicated with the exhaust outlet pipe through the first, second, and third silencing chambers in this order.

A system may include a tube through which hot fluid is transported from one end to another, wherein the tube radiates heat energy and transfers heat energy to surrounding air by convection. The system may also include a reflector that reflects the radiated heat and a hood that captures the heat energy from the surrounding air through convection, wherein the hood radiates the captured heat energy. The reflector may include a bi-involute curved surface.

A torque converter comprising a torque input element (19), an impeller wheel (3) rotationally coupled to the torque input element (19) and able to hydrokinetically drive a turbine wheel (4), a torque output element (8), clutch means (10, 38) movable between an engaged position in which the torque input element (19) and the torque output element (8) are rotationally coupled through damping means (12, 43, 44, 45), and a disengaged position in which the torque input element (19) and the torque output element (8) are rotationally coupled through the impeller wheel (3) and the turbine wheel (4), with a first bearing (31) being axially mounted between the impeller wheel (3) and the reactor (5), with a second bearing (31') being axially mounted between the reactor (5) and the turbine wheel (4).

A torque converter, including: an axis of rotation; a cover arranged to receive torque from an engine and including a first indentation; an impeller shell fixedly secured to the cover; at least one impeller blade fixedly secured to the impeller shell; a turbine including a turbine shell and at least one turbine blade fixedly secured to the turbine shell; and a lock-up clutch including a first carrier plate fixedly secured to the cover and including a first protrusion disposed in the first indentation and a clutch plate non-rotatably connected to the first carrier plate.

The present invention relates to a lockup apparatus for a torque converter and aims to obtain a smooth relative movement of a equalizer plate with respect to a deformation of a drive plate. The drive plate 26 as an inlet sided rotating member is connected to a driven plate 22 as an outlet sided rotating member by means of damper springs 28 in a rotating direction. The damper spring 28 is constructed by a pair of divided parts 28A and 28B. An equalizer plate as an intermediate member 29 is arranged so as to slide rotatably on bearing parts 26-1 of the drive plate 26 and supporting parts 40 fixed to the equalizer plate 29 are arranged between the divided parts 28A and 28B of the damper springs 28. The bearing part 26-1 of the drive plate 26 has an outer peripheral surface 26-1a', of which arc shape has a center C' of a curvature which is offset from the center C of the arc shape of the inner peripheral surface 29a of the equalizer plate 29.

A hydraulic circuit supplies pressurized hydraulic fluid to and from a torque converter that is operatively associated with a lockup clutch. The torque converter is disposed upstream of an outlet regulator that maintains a predetermined pressure in the torque converter. Power transmission in a powertrain can be directed through the torque converter during a hydrodynamic mode and can be directed through the lockup clutch during lockup mode. To switch between the hydrodynamic mode and the lockup mode, the hydraulic circuit includes a diverter valve to selectively direct pressurized hydraulic fluid between the torque converter and the lockup clutch. When operating in the lockup mode, the diverter valve further diverts hydraulic fluid discharged for the torque converter to bypass the outlet regulator disposed downstream of the torque converter.

A lockup clutch for a torque converter is provided. The lockup clutch includes a clutch plate and a piston assembly. The piston assembly includes a base section and a shim fixed to the base section. The shim is arranged for contacting the clutch plate to cause engagement of the lockup clutch. A method of forming a lockup clutch is also provided. The method includes fixing a shim to a base section to form a piston assembly; and arranging the piston assembly adjacent to a clutch plate such that the shim is arranged for contacting the clutch plate to cause engagement of the lockup clutch. A torque converter is also provided.

A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.

An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.