Compositions and methods for adjustable lenses are provided. In some embodiments, the lenses contain a lens matrix material, a masking compound, and a prepolymer. The lens matrix material provides structure to the lens. The masking compound is capable of blocking polymerization or crosslinking of the prepolymer, until photoisomerization of the compound is triggered, and the compound is converted from a first isomer to a second isomer having a different absorption profile. The prepolymer is a composition that can undergo a polymerization or crosslinking reaction upon photoinitiation to alter one or more of the properties of the lenses.

The present disclosure provides a method of providing an adhesive composition comprising the steps of combining crosslinkable composition including: a) a (meth)acryloyl monomer mixture with the b) photocrosslinking agent mixture, and irradiating with UVC radiation to polymerize and crosslink the composition.

This disclosure provides a network security architecture that permits installation of different software security products as virtual machines (VMs). By relying on a standardized data format and communication structure, a general architecture can be created and used to dynamically build and reconfigure interaction between both similar and dissimilar security products. Use of an integration scheme having defined message types and specified query response framework provides for real-time response and easy adaptation for cross-vendor communication. Examples are provided where an intrusion detection system (IDS) can be used to detect network threats based on distributed threat analytics, passing detected threats to other security products (e.g., products with different capabilities from different vendors) to trigger automatic, dynamically configured communication and reaction. A network security provider using this infrastructure can provide hosted or managed boundary security to a diverse set of clients, each on a customized basis.

In embodiments of driver interface functions to interface client function drivers, a set of serial communication protocol driver interfaces are exposed by a core driver stack, and the serial communication protocol driver interfaces include driver interface functions to interface with client function drivers that correspond to client devices configured for data communication in accordance with the serial communication protocol. A client function driver can check for the availability of a driver interface function before interfacing with the core driver stack via the serial communication protocol driver interfaces. A contract version identifier can also be received from the client function driver via an extension of the driver interface functions, where the contract version identifier indicates a set of operation rules by which the client function driver interfaces with the core driver stack.

In one exemplary embodiment, a computer-implemented method includes receiving, at a remote direct memory access (RDMA) device, a plurality of RDMA requests referencing a plurality of virtual pages. Data transfers are scheduled for the plurality of virtual pages, wherein the scheduling occurs at the RDMA device. The number of the virtual pages that are currently pinned is limited for the RDMA requests based on a predetermined pinned page limit.

A dispersed storage network memory includes a pool of storage nodes, where the pool of storage nodes stores a multitude of encoded data files. A storage node obtains and analyzes data access response performance data for each of the storage nodes to produce a modified data access response plan that includes identity of an undesired performing storage node and an alternative data access response for the undesired performing storage node. The storage nodes receive corresponding portions of a data access request for at least a portion of one of the multitude of encoded data files. The undesired performing storage node or another storage node processes one of the corresponding portions of the data access request in accordance with the alternative data access response.

Machines, systems and methods for I/O monitoring in a plurality of compute nodes and a plurality of service nodes utilizing a Peripheral Component Interconnect express (PCIe) are provided. In one embodiment, the method comprises assigning at least one virtual function to a services node and a plurality of compute nodes by the PCIe interconnect and a multi-root I/O virtualization (MR-IOV) adapter. The MR-IOV adapter enables bridging of a plurality of compute node virtual functions with corresponding services node virtual functions. A front-end driver on the compute node requests the services node virtual function to send data and the data is transferred to the services node virtual function by the MR-IOV adapter. A back-end driver running in the services node receives and passes the data to a software service to modify/monitor the data. The back-end driver sends the data to another virtual function or an external entity.

Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate. A transfer rate at which the storage device transfers data is set to the selected recording medium transfer rate.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

A data storage device includes a first memory device configured to store data having a first property, a second memory device configured to store data having a second property, and a controller. The controller selects data stored in the first memory device, and transfers the selected data to the second memory device or stores the selected data in another physical location of the first memory device selectively depending on an update count (UC) of an address at which the selected data is stored.

The various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). In one aspect, a portion of memory (e.g., a page in a block of a flash memory device) may be programmed many (e.g., 1000) times before an erase is required. Some embodiments include systems, methods and/or devices to integrate Bloom filter functionality in a non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to an unused location in the memory.

Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plurality of functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.

An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

A method, apparatus, and system for switching from an existing target end device to a next target end device in a multi-expander storage topology by using Fast Context Switching. The method enhances Fast Context Switching by allowing Fast Context Switching to reuse or extend part of an existing connection path to an end device directly attached to a remote expander. The method can include reusing or extending at least a partial path of an established connection between an initiator and the existing target end device for a connection between the initiator and the next target end device, whereby the existing target end device and the next target end device are locally attached to different expanders.

A system, method and computer-readable media for managing a compute environment are disclosed. The method includes importing identity information from an identity manager into a module performs workload management and scheduling for a compute environment and, unless a conflict exists, modifying the behavior of the workload management and scheduling module to incorporate the imported identity information such that access to and use of the compute environment occurs according to the imported identity information. The compute environment may be a cluster or a grid wherein multiple compute environments communicate with multiple identity managers.

A system, method and computer program product for allocating shared resources. Upon receiving requests for resources, the cost of bundling software in a virtual machine (VM) image is automatically generated. Software is selected by the cost for each bundle according to the time required to install it where required, offset by the time to uninstall it where not required. A number of VM images having the highest software bundle value (i.e., highest cost bundled) is selected and stored, e.g., in a machine image store. With subsequent requests for resources, VMs may be instantiated from one or more stored VM images and, further, stored images may be updated selectively updated with new images.

Embodiments of the invention are directed to a system, method, or computer program product for providing an information technology build service for building a platform in response to a service request. The invention receives a service request for the platform build from a requester, receives a plurality of platform parameters from the requester, determines whether the service request requires one or more physical machines or one or more virtual machines, and if the service request requires one or more virtual machines, initiates build of the one or more virtual machines. The invention also provisions physical and virtual storage based on received parameters, provisions physical and virtual processing power based on received parameters, and manages power of resources during the build, the managing comprising managing power ups, power downs, standbys, idles and reboots of one or more physical components being used for the build.

A system for protecting an electronic device against malware includes a memory, an operating system configured to execute on the electronic device, and a below-operating-system security agent. The below-operating-system security agent is configured to trap an attempted access of a resource of the electronic device, access one or more security rules to determine whether the attempted access is indicative of malware, and operate at a level below all of the operating systems of the electronic device accessing the memory. The attempted access includes attempting to write instructions to the memory and attempting to execute the instructions.

A system and method for reconfiguring a computing environment comprising a consumption analysis server, a placement server, an infrastructure management client and a data warehouse in communication with a set of data collection agents and a database. The consumption analysis server operates on measured resource utilization data to yield a set of resource consumptions in regularized time blocks, collects host and virtual machine configurations from the computing environment and determines available capacity for a set of target hosts. The placement server assigns a set of target virtual machines to the target set of hosts in a new placement. In one mode of operation the new placement is nearly optimal. In another mode of operation, the new placement is “good enough” to achieve a threshold score based on an objective function of resource capacity headroom. The new placement is implemented in the computing environment.

A system and method for reordering storage levels in a virtualized environment includes identifying a virtual machine (VM) to be transitioned and determining a new storage level order for the VM. The new storage level order reduces a VM live state during a transition, and accounts for hierarchical shared storage memory and criteria imposed by an application to reduce recovery operations after dynamic resource allocation actions. The new storage level order recommendation is propagated to VMs. The new storage level order applied in the VMs. A different storage-level order is recommended after the transition.

Method and system are provided for managing components of a storage operating environment having a plurality of virtual machines that can access a storage device managed by a storage system. The virtual machines are executed by a host platform that also executes a processor-executable host services module that interfaces with at least a processor-executable plug-in module for providing information regarding the virtual machines and assists in storage related services, for example, replicating the virtual machines.

An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

The technology of the present application provides a networked computer system with at least one workstation and at least one shared resource such as a database. Access to the database by the workstation is managed by a database management system. An access engine reviews job requests for access to the database and allows job requests access to the resource based protocols stored by the system.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

1,4 fullerene deriatives useful for solar cells are provided, where their structures allow for straightforward functionalizations to tune their properties in terms of solubility and LUMO energy levels.

The present invention is directed to a combination reactor system for exothermic reactions comprising a trickle-bed reactor and a shell-and-tube reactor. This combination allows the system to efficiently remove heat while also providing the ability to control both the temperature and/or reaction progression. The trickle-bed reactor removes heat efficiently from the system by utilizing latent heat and does not require the use of a cooling or heating medium. The shell-and-tube reactor is used to further progress the reaction and provides a heat exchanger in order to introduce fluid at the desired temperature in the shell-and-tube reactor. Also, additional reactant or reactants and/or other fluids may be introduced to the shell-and-tube section of the reactor under controlled temperature conditions.

Disclosed is a process for the synthesis of 1,1,2,3-tetrachloropropene (HCC-1230xa) using 1,1,3-trichloropropene (HCC-1240za) and/or 3,3,3-trichloropropene (HCC-1240zf) and Cl2 gas as the reactants, wherein the process takes place in a single reactor system. Before this invention, HCC-1230xa was made in a two-step process using HCC-1240za/HCC-1240zf and Cl2 gas, and the processing was conducted using two separate reactors.

The invention is directed to a catalyst for the gas phase fluorination of 1,1,2-trichloroethane and/or 1,2-dichloroethene with HF to give 1-chloro-2,2-difluoroethane which catalyst is prepared by co-depositing FeCl3 and MgCl2 on chromia-alumina, or co-depositing Cr(NO3)3 and Ni(NO3)2 on active carbon, or by doping alumina with ZnCl2, and to a process for the preparation of 1-chloro-2,2-difluoroethane comprising a catalytic gas phase fluorination of 1,1,2-trichloroethane and/or 1,2-dichloroethene wherein one of the catalysts according to claim 2 or 3 is used.

Disclosed is a reactor and agitator useful in a high pressure process for making 1-chloro-3,3,3-trifluoropropene (1233zd) from the reaction of 1,1,1,3,3-pentachloropropane (240fa) and HF, wherein the agitator includes one or more of the following design improvements: (a) double mechanical seals with an inert barrier fluid or a single seal;(b) ceramics on the rotating faces of the seal;(c) ceramics on the static faces of seal;(d) wetted o-rings constructed of spring-energized Teflon and PTFE wedge or dynamic o-ring designs; and(e) wetted metal surfaces of the agitator constructed of a corrosion resistant alloy.

The present invention provides a method for separating halocarbons. In particular, the invention provides a method for separating halogenated olefin impurities from 2-chloro-1,1,1,2-tetrafluoropropane (HCFC-244bb) using a solid adsorbent, particularly activated carbon. More particularly the invention pertains to a method for separating 2-chloro-3,3,3-trifluoro-propene (HCFO-1233xf) from HCFC-244bb, which are useful as intermediates in the production of 2,3,3,3-tetrafluoropropene (HFO-1234yf).

Fluorinated aromatic materials, their synthesis and their use in optoelectronics. In some cases, the fluorinated aromatic materials are perfluoroalkylated aromatic materials that may include perfluoropolyether substituents.

A heat transfer fluid emulsion includes a heat transfer fluid, and liquid droplets dispersed within the heat transfer fluid, where the liquid droplets are substantially immiscible with respect to the heat transfer fluid and have dimensions that are no greater than about 100 nanometers. In addition, the thermal conductivity of the heat transfer fluid emulsion is greater than the thermal conductivity of the heat transfer fluid.

According to the present invention, a metal nanoparticle dispersion suitable to multiple layered coating by jetting in the form of fine droplets is prepared by dispersing metal nanoparticles having an average particle size of 1 to 100 nm in a dispersion solvent having a boiling point of 80° C. or higher in such a manner that the volume percentage of the dispersion solvent is selected in the range of 55 to 80% by volume and the fluid viscosity (20° C.) of the dispersion is chosen in the range of 2 mPa·s to 30 mPa·s, and then when the dispersion is discharged in the form of fine droplets by inkjet method or the like, the dispersion is concentrated by evaporation of the dispersion solvent in the droplets in the course of flight, coming to be a viscous dispersion which can be applicable to multi-layered coating.

A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.

A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing apparatus also includes another execution unit which performs computation on two operand inputs, one of which is selectable between read data from a register and an immediate value, and the other of which is an immediate value. A control unit determines, based on a received instruction specifying a computation on two operands, whether each of the two operands specifies read data from a register or an immediate value. Depending on the determination result, the control unit causes one of the execution units to execute the computation specified by the received instruction.

A method is disclosed which may include analyzing communication requests in a business process between a client and a server offering a service application to be tested. The method may further include identifying a call to a web service in the analyzed communication. The method may also include determining a location of a Web Service Description Language (WSDL) file relating to the web service on a remote server and downloading the WSDL file from the determined location. A computer readable medium having stored thereon instructions for performing the method and a computer system are also disclosed.