An upright adaptor for a ladder tree stand converts that ladder tree stand into an upright tree stand. The adaptor includes a ladder stand base support which is attachable to the base of a tree and which receives the lower end of the ladder stand. A speed lock assembly is part of the upright adaptor and is attachable to an upper portion of the ladder tree stand. It includes a self-tapping screw and a double-acting ratchet wrench which is operable by a person standing on the ground once the ladder tree stand has been erected.

A debris passage for a cooling box of a work vehicle. Airflow is provided into the cooling box from the exterior environment. A plurality of heat exchangers transfer heat into the airflow. The debris passage is defined between opposing heat exchangers to permit debris to pass from the airflow to the exterior of the cooling box. In one embodiment, the debris passage is underneath an air mover and is substantially vertical.

A sensor signal processing device includes an AD conversion section, a filter section, a timing signal generation section, and an arithmetic section. The timing signal generation section generates a signal synchronized with a crank angle of an engine based on a signal indicating the crank angle and generates a data acquisition timing signal by compensating the signal synchronized with the crank angle with a delay time of the filter. The arithmetic section acquires a plurality of sensor signals, which is transmitted from a sensor, converted from an analog signal to a digital signal by the AD conversion section, and filtered by the filter section, in a term before and after receiving the data acquisition timing signal and generates a data synchronized with the data acquisition timing signal.

A control apparatus for an internal combustion engine having a means for performing a model calculation to calculate, as an exhaust temperature calculation value, the temperature of exhaust gas in an exhaust branch tube at the time of starting an engine, using a model representing the temperature behavior of the exhaust gas in the exhaust branch tube during stop of an engine; and an exhaust temperature actual measurement value output means for detecting the temperature of exhaust gas in the exhaust branch tube, and outputting the detected temperature as an exhaust temperature actual measurement value, wherein the model includes at least one parameter.

A valve operating device for an engine is provided. The device includes a cam element formed with an end face cam in one end thereof, and a control member driven by an actuator to project to an actuated position at which the control member is projected to engage with the end face cam so as to move the cam element in one of the axial directions, and retreat to a non-actuated position at which the control member is retreated from the actuated position. The cam element has a slope inclining in a circumferential direction of the cam element and for, when the control member is at the actuated position, sliding in contact with a contact part provided at the control member so as to forcibly move the control member back to the non-actuated position after the movement of the cam element via the end face cam is finished.

A variable valve lift apparatus may include a rocker arm coupled with a rocker arm shaft, a valve bridge disposed to be pressed by one end portion of the rocker arm, the valve bridge including a piston insertion hole and at least one pin insertion hole connecting to the piston insertion hole, a valve disposed to be pressed by the valve bridge, and a variable lift unit disposed in the valve bridge and variably controlling an amount that the rocker arm presses the valve bridge. The variable lift unit includes a variable piston of which the lower portion is inserted into the piston insertion hole, and a check pin disposed in the pin insertion hole to be selectively inserted into the pin groove formed on a side surface of the variable piston according to the hydraulic pressure supplied to the piston oil passage formed in the variable piston.

An intake control system for a multi-cylinder combustion engine with control valves positioned within intake passageways that can vary the cross-sectional area of the intake runners to increase air intake velocity at low engine speeds. The control system includes an inner frame that can be inserted into a lower manifold after manufacture. The inner frame includes a plurality of flapper valves that are actuated by a four-bar link design, which is driven by a hypoid gear-set. The control system controls an internal DC electric motor that actuates a worm-drive gear-set, which in turn drives the hypoid gear-set to either engage or retract the flapper valves within the intake passageways.

Disclosed is an engine that comprises an engine block, and the engine block comprises a cylinder. The engine further comprises a cylinder head mounted to the engine block, and the cylinder head comprises an intake valve seat and a shroud. Further yet, the engine comprises a combustion chamber formed at least partially by the cylinder and the cylinder head. The intake valve is configured to travel between a fully closed position seated against the intake valve seat and an opened position displaced from the intake valve seat, thus allowing intake flow through the intake valve seat into the combustion chamber. The shroud only partially surrounds a periphery of the valve and extends along at least a portion of the travel of the intake valve so as to restrict intake flow along only a portion of the intake valve.

A fuel feed device for attachment to a cylinder head of an internal combustion engine has at least one fuel distribution element extending along a longitudinal direction, and at least one connecting element extending transversely to the longitudinal direction, wherein the connecting element can be used to connect the fuel distribution element to the cylinder head. The fuel feed device further includes at least one reinforcing element which is connected, on one hand, to an outer surface of the fuel distribution element and, on the other hand, to the connecting element outside the fuel distribution element.

A device for injecting fuel over a cylinder head of an engine, including a tubular body, an injection nozzle forming an extension of the tubular body, a needle extending coaxially to the nozzle in a form of a rod, an end of which includes a head forming a valve on a seat supported by the injection nozzle, and an actuator configured to cause a movement of the head so as to open the valve, the needle configured to axially resonate when the same is subjected to axial pulses at a predetermined nominal frequency by the actuator. A system for mounting the device includes a spacer for bearing on the cylinder head, as well as on a front surface of the tubular body at the connection to the nozzle.

A fastening structure of a fuel delivery pipe and a cylinder head of an internal combustion engine includes three or more bosses provided on each of the cylinder head and the fuel delivery pipe, and fastening portions formed by bolting the bosses on the cylinder head to the bosses on the fuel delivery pipe. The fastening portions at both end portions of the fuel delivery pipe are less rigid than one or more fastening portions in a middle between the fastening portions positioned at both end portions of the fuel delivery pipe.

An exhaust gas recirculation device is provided. The device recirculates, from an exhaust system to an intake system, a part of exhaust gas from a plurality of cylinders of a multi-cylinder engine as EGR gas. The device includes a single EGR pipe extending from the exhaust system toward the intake system, an EGR manifold branching from a downstream end portion of the EGR pipe toward each cylinder, and an EGR valve for adjusting an EGR gas amount. The EGR manifold has one or more common EGR passages having a single pipe portion and branched pipe portions, and one or more independent EGR passages. Each shape of the common and independent EGR passages is set so that a communicating path in the EGR manifold communicating an arbitrary cylinder with a cylinder where combustion is performed subsequently thereto has the same volume for any cylinder combination having the adjacent combustion order.

Embodiments of systems and methods for tuning a turbine are provided. In one embodiment, a method may include receiving at least one of a measured operating parameter or a modeled operating parameter of a turbine during operation; and tuning the turbine during operation. The turbine may be tuned during operation by applying the measured operating parameter or modeled operating parameter or parameters to at least one operational boundary model, applying the measured operating parameter or modeled operating parameter or parameters to at least one scheduling algorithm, comparing the output of the operational boundary model or models to the output of the scheduling algorithm or algorithms to determine at least one error term, and closing loop on the one error term or terms by adjusting at least one turbine control effector during operation of the turbine.

In an engine having a plurality of cylinders in which a plurality of fuel injection valves are provided respectively, fuel is injected at a predetermined injection ratio, and an abnormality of air-fuel ratio variation is detected. If a fuel injection amount of at least one of the plurality of the fuel injection valves is smaller than a predetermined reference value, the fuel injection amount is increased so as to become equal to or larger than the reference value.

A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

A first communication device and method therein for transmitting data information at fixed time instants on a radio channel to a second communication device in a radio communications network. First, the first communication device determines that the radio channel is available for transmitting data information to the second communication device during a time period determined by the first communication device. Then, the first communication device transmits a preamble on the available radio channel after the time period. The first communication device thereafter transmits the data information on the available radio channel to the second communication device at a next fixed time instant following the transmission of the preamble.

Disclosed are a method and an apparatus for generating a codeword, and a method and an apparatus for recovering a codeword. An encoder calculates the number of punctured symbol nodes among symbol nodes included in a codeword, punctures symbol nodes located at even or odd number positions among the symbol nodes included in the codeword, calculates the number of symbol nodes which need to be additionally punctured on the basis of the calculated number of the symbol nodes to be punctured, classifies the symbol nodes, which need to be additionally punctured, into one or more punctured node groups on the basis of the calculated number of symbol nodes which need to be punctured, determines the locations on the codeword where the one or more punctured node groups are to be arranged, and punctures the symbol nodes included in the codeword which belong to the punctured node groups according to the determined locations. A transmission unit transmits the codeword.