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Twenty-four projects can be viewed online at newkensington.psu.edu/virtual-research-expo.

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Goals from Casemiro and Isco helped Real Madrid successfully defend their title but Manchester United gave the European champions a scare after Romelu Lukaku pulled one back.

Watch highlights from all the action at the Under-17 Euro in England, including the Netherlands' dramatic final triumph against Italy.

The Netherlands came out on top after a busy fortnight of action in the Republic of Ireland.

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Researchers in Penn State’s College of Engineering, College of Agricultural Sciences and College of Medicine say direct LTP treatment and plasma-activated media are effective treatments against bacteria found in liquid cultures and have devised a way to create plasma directly in liquids.

With the spread of COVID-19, Penn State’s Social Science Research Institute has launched a new website that provides resources for researchers, policy-makers and the general public to inform and to address impacts of the pandemic — with a focus on its broader implications for individuals, families, communities, and the commonwealth.

Dover is unlocking the potential of its historic downtown with a new marketing campaign highlighting opportunities for small business owners ready to take their business dreams to the next level. State and local officials led by Gov. John Carney; Linda Parkowski, acting director of the Delaware Division of Small Business and Dover Mayor Robin Christiansen […]

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More photographs from the 2018 Delaware State Fair are available on Flickr. DOVER, Del. — Many Delaware youth and adult exhibitors are ready to showcase their agricultural exhibits at this year’s Delaware State Fair. Along with rides, food, and games, the state fair is a great opportunity for fair-goers to learn more about agriculture – […]

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FOR IMMEDIATE RELEASE Media Contacts: Cynthia Cavett, Marketing Specialist & Public Information Officer Delaware Office of Highway Safety Cynthia.Cavett@delaware.gov 302-744-2743 DOVER, Del. (September 15, 2019) – Child Passenger Safety Week is a vital awareness campaign that runs nationwide to promote kids being secured in the right car seat for their age, height, and weight. This […]

I was recently honored to share the stage with government and medical leaders to discuss ways to impact the nation’s opioid epidemic. Hosted by The Washington Post, this event included often spirited conversations on ways to solve this national crisis. As the medical director for SAS US Government, I have [...]

The post Washington Post, new SAS user group, highlight need to collaborate on opioid epidemic appeared first on Government Data Connection.

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Indian Budget 2020 Highlights - 10 Key Announcements

In 1985, as a relatively new editor at Computer Design magazine, I was asked to go forth and cover a new business called CAE (computer-aided engineering). I knew nothing about it, but I had been writing about design for test, so there seemed to be somewhat of a connection. Little did I know that “CAE” would turn into “EDA” and that I’d write about it for the next 30 years, for Computer Design, EE Times, Cadence, and a few others.

Now that I’m about to retire, I’m looking back over those 30 years. What a ride it has been! By the numbers I covered 31 Design Automation Conferences (DACs), hundreds of new products, dozens of acquisitions and startups, dozens of lawsuits, and some blind alleys that didn’t work out (like “silicon compilation”). Chip design went from gate arrays and PLDs with a few thousand gates to processors and SoCs with billions of transistors.

In 1985 there were three big CAE vendors – Daisy Systems, Mentor Graphics, and Valid Logic. All sold bundled packages that included workstations and CAE software; in fact, Daisy and Valid designed and manufactured their own workstations. In the early 1980s a workstation with schematic capture and gate-level logic simulation might have set you back $120,000. In 1985 OrCAD, now part of Cadence, came out with a $500 schematic capture package running on IBM PCs.

Cadence and Synopsys emerged in the late 1980s, and by the 1990s the EDA industry was pretty much a software-only business (apart from specialized machines like simulation accelerators). Since the early 1990s the “big three” EDA vendors have been Cadence, Synopsys, and Mentor, giving the industry stability but allowing for competition and innovation.

Here, in my view, are some of the highlights that occurred during the past 30 years of EDA.

EDA is a Highlight

The biggest highlight in EDA is the existence of a commercial EDA industry! Marching hand in hand with the fabless semiconductor revolution, commercial EDA made it possible for hundreds of companies to design semiconductors, as opposed to a small handful that could afford large internal CAD operations and fabs. With hundreds of semiconductor companies as opposed to a half-dozen, there’s a lot more creativity, and you get the level of sophistication and intelligence that you see in your smartphone, video camera, tablet, gaming console, and car today.

CAE + CAD = EDA. This is not just a terminology issue. By the mid-1980s it became clear that front-end design (CAE) and physical design (CAD) belonged together. The big CAE vendors got involved in IC and PCB CAD, and presented increasingly integrated solutions. People got tired of writing “CAE/CAD” and “EDA” was born.

The move from gate-level design to RTL. This move happened around 1990, and in my view this is EDA’s primary technology success story during the past 30 years. Moving up in abstraction made the design and verification of much larger chips possible. Going from gate-level schematics to a hardware description language (HDL) revolutionized logic design and verification. Which would you rather do – draw all the gates that form an adder, or write a few lines of code and let a synthesis tool find an adder in your chosen technology?

Two developments made this shift in design possible. One was the emergence of commercial RTL synthesis (or “logic synthesis”) tools from Synopsys and other companies, which happened around 1990. Another was the availability of Verilog, developed by Gateway Design Automation and purchased by Cadence in 1989, as a standard RTL HDL. Although most EDA vendors at the time were pushing VHDL, designers wanted Verilog and that’s what most still use (with SystemVerilog coming on strong in the verification space).

IC functional verification underwent huge changes in the late 1990s and early 2000s, largely due to new technology developed by Verisity, which was acquired by Cadence in 2005. Before Verisity, verification engineers were writing and running directed tests in an ad-hoc manner. Verisity introduced or improved technologies such as pseudo-random test generation, coverage metrics, reusable verification IP, and semi-automated verification planning. The Verisity “e” language became a widely used hardware verification language (HVL).

The biggest way that EDA has expanded its focus has been through semiconductor IP. Today Synopsys and Cadence are leading providers in this area. Thanks to the availability of design and verification IP, many SoC designs today reuse as much as 80% of previous content. This makes it much, much faster to design the remaining portion. While IP began with fairly simple elements, today commercially available IP can include whole subsystems along with the software that runs on them. With IP, EDA vendors are providing not only design tools but design content.

Finally, the EDA industry has done an amazing job of keeping up with SoC complexity and with advanced process nodes. Thanks to intense and early collaboration between foundries, IP, and EDA providers, tools and IP have been ready for process nodes going down to 10nm.

Where Does ESL Fit?

In some ways, electronic system level (ESL) design is both a lowlight and a highlight. It’s a lowlight because people have been talking about it for 30 years and the acceptance and adoption have come very slowly. ESL is a highlight because it’s finally starting to happen, and its impact on design and verification flows could be dramatic. Still, ESL is vaguely defined and can be used to describe almost anything that happens at a higher abstraction level than RTL.

High-level synthesis (HLS) is an ESL technology that is seeing increasing use in production environments. Current HLS tools are not restricted to datapaths, and they produce RTL code that gives better quality of results than hand-written RTL. Another ESL methodology that’s catching on is virtual prototyping, which lets software developers write software pre-silicon using SystemC models. Both HLS and virtual prototyping are made possible by the standardization of SystemC and transaction-level modeling (TLM). However, it’s still not easy to use the same SystemC code for HLS and virtual prototyping.

And Now, Some Lowlights

Every new industry has some twists and turns, and EDA is no exception. For example, the EDA industry in the 1980s and 1990s sparked a lot of lawsuits. At EE Times my colleagues and I wrote a number of articles about EDA legal disputes, mostly about intellectual property, trade secrets, or patent issues. Over the past decade, fortunately, there have been far fewer EDA lawsuits than we had before the turn of the century.

Another issue that was troublesome in the 1980s and 1990s was so-called “standards wars.” These would occur as EDA vendors picked one side or the other in a standards dispute. For example, power intent formats were a point of conflict in the early 2000s, but the Common Power Format (CPF) and the Unified Power Format (UPF) are on the road to convergence today with the IEEE 1801 effort. As mentioned previously, Verilog and VHDL were competing for adoption in the early 1990s. For the most part, Verilog won, showing that the designer community makes the final decision about which standards will be used.

How on earth did there get to be something like 30 DFM (design for manufacturability) companies 10-12 years ago? To my knowledge, none of these companies are around today. A few were acquired, but most simply faded away. A lot of investors lost money. Today, VCs and angel investors are funding very few EDA or IP startups. There are fewer EDA startups than there used to be, and that’s too bad, because that’s where a lot of the innovation comes from.

Here’s another current lowlight -- not enough bright engineering or computer science students are joining EDA companies. They’re going to Google, Apple, Facebook, and the like. EDA is perceived as a mature industry that is still technically very difficult. We need to bring some excitement back into EDA.

Where Is EDA Headed?

Now we come to what you might call “headlights” and look at what’s coming. My list includes:

• System Design Enablement. This term has been coined by Cadence to describe a focus on whole systems or end products including chips, packages, boards, embedded software, and mechanical components. There are far more systems companies than semiconductor companies, leaving a large untapped market that’s looking for solutions.
• New frontiers for EDA. At a 2015 Design Automation Conference speech, analyst Gary Smith suggested that EDA can move into markets such as embedded software, mechanical CAD, biomedical, optics, and more.
• Vertical markets. EDA has until now been “horizontal,” providing the same solution for all market segments. Going forward, markets like consumer, automotive, and industrial will have differing needs and will need optimized tools and IP.
• Internet of Things. This is a current buzzword, but the impact on EDA remains uncertain. Many IoT devices will be heavily analog, use mature process nodes, and be dirt cheap. Lip-Bu Tan, Cadence CEO, recently pointed out that the silicon percentage of IoT revenue will be small and that a lot of the profits will be on the service side.

Moving On

For the past six years I’ve been writing the Industry Insights blog at Cadence.com. All things change, and with this post comes a farewell – I am retiring in late June and will be pursuing a variety of interests other than EDA. I’ll be watching, though, to see what happens next in this small but vital industry. Thanks for reading!

Richard Goering

I could not find info about the highlight shapes/layers in the cadence doc directory, forum, support library.

I have a script that creates highlight shapes on the y* drawing layer.

My understand is the highlight is a virtual shape. The shapes go away when the cadence session is closed or when you close data of that cellview if it is not global.

If they are vitual shapes it would be okay to use valid or process layers when I create the highlight set with geCreateHilightSet.

Ex: ( The command I use to create the hiighlight set       geCreateHilightSet(cv list(lay purp) nil) )

Current y0-9 drawing 

To N-P_implant drawing

Paul

FDI into Latvia has recovered in recent years as the Baltic state has implemented stricter anti-money laundering procedures. Latvian minister of economics Ralfs Nemiro talks to Alex Irwin-Hunt about the progress made.

Southeast Asia is poised for a long-overdue and much-needed boom in solar.

The advice that Pennwell’s 2014 Woman of the Year, Mary Powell, gave to women in the power industry during Tuesday’s Women in Power Luncheon might come as a surprise to some. It was this: Stop undercutting each other. Powell said the most difficult obstacles she has encountered in her various leadership roles have not come from men, but rather from other women. Small comments like “I don’t know how you do it [being a mom and holding a high-level job]”, serve to bring doubt and uncertainty to high achieving women in any industry, and ultimately can lead to women exiting their careers in order to fit what they perceive is the societal norm.

The advice that Pennwell’s 2014 Woman of the Year, Mary Powell, gave to women in the power industry during Tuesday’s Women in Power Luncheon might come as a surprise to some. It was this: Stop undercutting each other. Powell said the most difficult obstacles she has encountered in her various leadership roles have not come from men, but rather from other women. Small comments like “I don’t know how you do it [being a mom and holding a high-level job]”, serve to bring doubt and uncertainty to high achieving women in any industry, and ultimately can lead to women exiting their careers in order to fit what they perceive is the societal norm.

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Keynote speaker – Challenges in the Food & Drink Industry   Annus horribilis; the year of the chicken On Tuesday 2 December, Eversheds hosted its annual Food and Drink conference, which opened with a keynote speech by the hugely ...

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Bank-held nonperforming loans in some Asian economies have risen in recent years. Policy makers should address this growing risk now.

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Hunger and malnutrition were an increasing problem worldwide before the pandemic. Restrictions imposed to curb disease spread have disrupted local and international food supply chains, making the problem even more urgent.

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