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Unable to add wire bond finger from die pins

By feedproxy.google.com
Published On :: Wed, 29 Jan 2020 11:54:40 GMT

I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. 


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Sunday Brunch Video for 3rd May 2020

By community.cadence.com
Published On :: Sun, 03 May 2020 12:00:00 GMT

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]


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BoardSurfers: Training Insights - Fundamentals of PDN for Design and PCB Layout

By feedproxy.google.com
Published On :: Wed, 22 Apr 2020 02:31:00 GMT

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)


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Sparam resonance tuning problem

By feedproxy.google.com
Published On :: Sun, 15 Mar 2020 22:17:10 GMT

Hello, I am trying to use two inductors in my LNA as shown bellow to have a S-PARAM response so i will have S11 with lowerst possible values and tweak them for matching network. However when i ran EXPLORER live tuning with SParam as shown bellow i get no change in the response.

I know that Cgs and Cgd with the inductors having a resonance so by Varying L value i should have seen the change in resonance location,

But there is no change.Where did i go wrong?

Thanks. 


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Kf parameter testing in spectre under non standart conditions

By feedproxy.google.com
Published On :: Tue, 31 Mar 2020 19:02:42 GMT

Hello, i need to test the  parameter Kf under some conditions in subthreshold.i cannot just plot the OP param,becasue i need to derive it under certain conditions.

Spectre(of Cadence) like BSIM(of Berkley) has developed a method for deriving each parameter in their model.

Is there a way to help me with such manual where i can test in cadence virtuoso the Kf parameter shown in the formula bellow?

Thanks.


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E- (SPMHDB-187): SHAPE boundary may not cross itself.

By feedproxy.google.com
Published On :: Mon, 24 Feb 2020 07:26:13 GMT

Hi experts,

I have a problem with my design as below

ERROR: in SHAPE (-2.3622 2.3622)

  class = ETCH
  subclass = TOP 
  Part of Symbol Def SHAPE_4725X4725.
      Which is part of a padstack as a SHAPE symbol.
  ERROR(SPMHDB-187): SHAPE boundary may not cross itself.
   Error cannot be fixed.
       Object has first point location at (-2.3622 2.3622).

Can you tell me how to solve my problem?

Thanks a lot.


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Skill code to Calculating PCB Real-estate usage using placement boundaries and package keep ins

By feedproxy.google.com
Published On :: Wed, 04 Mar 2020 18:37:43 GMT

Other tools allow a sanity check of placement density vs available board space.  There is an older post "Skill code to evaluate all components area (Accumulative Place bound area)"  (9 years ago) that has a couple of examples that no longer work or expired.

This would be useful to provide feedback to schismatic and project managers regarding the component density on the PCB and how it will affect the routing abilities.  Thermal considerations can be evaluated as well 

Has anyone attempted this or still being done externally in spread sheets?


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How to call a skil file in the other skill file to create one new function.

By feedproxy.google.com
Published On :: Mon, 20 Apr 2020 11:05:56 GMT

Hi guys,

eDave,

I need to call (replay) a skill to combine some skills to ONE UI for more convenience and using as more easier.

Please help me to find the command to execute this.(code for example as more good)

HT,


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How to run a regressive test and merge the ncsim.trn file of all test into a single file to view the waveform in simvision ?

By feedproxy.google.com
Published On :: Mon, 13 Jan 2020 12:04:01 GMT

Hi all,

         I want to know how to run a regressive test in cadence and merge all ncsim .trn file of each test case into a single file to view all waveform in simvision. I am using Makefile to invoke the test case.

         eg:-

               test0:

                     irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test0

             test1:

                   irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test1

          I just to call test0 followed by test1 or parallel both test and view the waveform for both tests case.

        I new to this tool and help me with it

                     


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Developing a solid DV flow : xrun wrapper tool

By feedproxy.google.com
Published On :: Sat, 18 Jan 2020 20:10:05 GMT

Hi all,

I need to develop a digital design/verification solution to compile,elaborate and simulate SV designs (basically a complex xrun wrapper). I am an experienced user of xrun and I have done a number of these wrappers over the years but this one is to be more of a tool, intented to be used Company-wise, so it needs to be very well thought and engineered.

It needs to be robust, simple and extensible. It needs to support multi-snapshot elaboration, run regressions on machine farms, collect coverage, create reports, etc.

I've been browsing the vast amount of documentation on XCELIUM and, although very good, I can't find any document which puts together all the pieces of what I am trying to achieve. I suppose I am more clear on the elaboration, compilation and simulation part but I am really lacking on the other areas like : LSF, regressions coverage, where does vManager fits in all this, etc.

I'd appreciate if someone can comment on whether there is a document which depicts how such a DV flow can be put together from scratch, or whether there is a kind of RAK with some example xrun wrapper.

Thanks


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Running xrun command in vsif file

By feedproxy.google.com
Published On :: Fri, 07 Feb 2020 10:11:37 GMT

Hi,

I found a basic Specman E/Verilog program at http://www.asic-world.com/examples/specman/memory.html and I would like to run it through a vsif file, with vManager.

I'm able to run it, without problems, with this command : xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e.

I wrote a first vsif which look like this:

---- vm_basic.vsif -----

session vm_basic {
        top_dir : /home/cadence/xrunTest/;
        output_mode: terminal;
};

group basic {
        test test {
                run_script: xrun -Q -unbuffered '-timescale' '1ns/1ns' '-access' '+rw' memory_tb.v mem_tb_top.e test_write_read_all.e
        };
};

----------------------------

This solution didn't work due to the prompt change with xrun, and I have no clue how to manage this issue.

Have you any idea?

Best regards,

Yohan


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trace ends from round to square?

By feedproxy.google.com
Published On :: Fri, 08 May 2020 15:18:24 GMT

Is it possible to change trace ends from round to square? Allegro PCB Designer 17.2 (basic)

Thanks


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VHDL-AMS std and ieee libraries not found/empty

By feedproxy.google.com
Published On :: Thu, 23 Apr 2020 17:53:15 GMT

I'm trying to set up a VHDL-AMS simulation, so I made a new cell, selected the vhdlamstext type, and copied some example from the web. But when I hit the save and compile button, I first got the following NOLSTD error:

https://www.edaboard.com/showthread.php?27832-Simulating-a-VHDL-design-in-ldv5-1

So I added said file to my cds.lib and tried again. But now I'm getting this:

ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cadappl/ictools/cadence_ic/6.1.7.721/tools/inca/files/STD.

If I go over to the Library Browser, it indeed shows that the library is completely empty. Properties show it has the following files attached.

In the file system I've also found a STD.src folder. Is there a way to recompile the library properly? Supposedly this folder includes precompiled versions, but looks like not really.


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ISF Function Extraction in Cadence Virtuoso

By feedproxy.google.com
Published On :: Mon, 27 Apr 2020 19:56:58 GMT

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.


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Unable to Import .v files with `define using "Cadence Verilog In" tool

By feedproxy.google.com
Published On :: Wed, 29 Apr 2020 00:12:42 GMT

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);


inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify


endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);


inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify


endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9


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Help!!, Spectre error: Illegal library definition found in netlist for TSMC 180nm

By feedproxy.google.com
Published On :: Mon, 04 May 2020 08:11:12 GMT

Dear All,
When I want to start simulation with spectre the error says:
Fatal error: Illegal library definition found in netlist
I set the model file correctly, but I don't know why it errors!
I opened the ADE>>Setup>>Model library
and I tried to modify the path of models file (SCS files)
It gives me "Illegal library definition found in netlist"
Thanks.


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ERROR (OSSGLD-18): and not able to run simulation

By feedproxy.google.com
Published On :: Wed, 06 May 2020 02:40:42 GMT

I put some stimulus in the simulation file section : 

_vpd_data_enb (pu_data_enb 0) vsource wave=[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl
_vpu_data_enb (pd_data_enb 0) vsource dc=pu_enb type=dc

I get the following error. 

ERROR (OSSGLD-18): The command character after '[' in the NLP expression '[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl

' is not a valid

character. The command character is the first character after '[' in the NLP

expression. It must be '?', '!', '#', '$', 'n', '@', '.', '~' or '+'. Enter a

valid character as the command character.

si: simin did not complete successfully.

 

I dont see anything wrong with the stimulus syntax


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News18 Urdu: Latest News Zunheboto

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visit News18 Urdu for latest news, breaking news, news headlines and updates from Zunheboto on politics, sports, entertainment, cricket, crime and more.


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News18 Urdu: Latest News Munger

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News18 Urdu: Latest News Una

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News18 Urdu: Latest News Jalaun

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RIP Chuni Goswami| প্রয়াত কিংবদন্তি ফুটবলার চুনী গোস্বামী

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News18 Urdu: Latest News Guna

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PM CARES Fundમાં રિલાયન્સ ઇન્ડસ્ટ્રીઝની 500 કરોડ આપવાની જાહેરાત, બે રાજ્યને 10 કરોડની સહાય

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Published On :: Monday, March 30, 2020 09:41 PM

રિલાયન્સ ઇન્ડસ્ટ્રીઝ ગુજરાત અને મહારાષ્ટ્ર મુખ્યમંત્રી રાહતનિધી ફંડમાં 5-5 કરોડ રૂપિયા આપશે. આગામી 10 દિવસ માટે 5 લાખ લોકોના ભોજનની પણ વ્યવસ્થા કરશે.


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કોરોનાથી દુનિયાભરમાં આર્થિક તબાહી આવશે, માત્ર ભારત અને ચીન બચશેઃ UN

By gujarati.news18.com
Published On :: Tuesday, March 31, 2020 03:18 PM

દુનિયાના ગરીબ અને વિકાસશીલ દેશોને આર્થિક મંદીથી ઉગારવા માટે લગભગ 2-3 ટ્રિલિયન ડૉલરની જરૂર પડશે


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Mutual Funds પર દબાણ વધ્યું, RBIએ 50 હજાર કરોડ રૂપિયા આપવાની કરી જાહેરાત

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Published On :: Monday, April 27, 2020 12:14 PM

યૂએસ બેઝ્ડ મ્યુચ્યુઅલ ફંડ હાઉસ ફ્રેન્કલિન ટેમ્પલટને ભારતમાં 6 Debt Fundsને બંધ કરી દેતાં રોકાણકારોના કરોડો રૂપિયા ફસાયા


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TV,ફ્રિઝ, AC ખરીદનારને Samsung આપી રહ્યું છે ભારે કેશબેક, નો કોસ્ટ EMIની સાથે મળશે આ ઓફર્સ

By gujarati.news18.com
Published On :: Tuesday, May 05, 2020 08:35 AM

લૉકડાઉન પુરૂં થતાની સાથે જ ટેલિવિઝન અને અન્ય ડિજિટલ એપ્લાયન્સ પર આજે અનેક લોભામણા ઓફરની જાહેરાત કરી છે.


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News18 Urdu: Latest News Yamunanagar

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News18 Urdu: Latest News Guntur

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News18 Urdu: Latest News Padrauna

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দেশ বিপর্যয়ের মুখে, এই সময় Reliance Foundation'-এর 'Mission Anna Seva' এক মহৎ উদ্যোগ: নীতা আম্বানি

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থাকছে Ultraviolet Tunnels, লকডাউন উঠলেই যাত্রী বিমান পরিষেবার জন্য তৈরি দিল্লি বিমানবন্দর

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News18 Urdu: Latest News Unnav

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Apple's Bug Bounty Opens For Business, $1M Payout Included

By packetstormsecurity.com
Published On :: Sat, 21 Dec 2019 06:48:57 GMT


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