In the world of power systems, synchronization and reactive power control are crucial to maintaining stability, efficiency, and reliability. Synchronizing various power sources, such as generators and grids, ensures they operate in harmony to meet the demand and support the... Read more

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Management requirement and information model for synchronization

Timing and synchronization aspects in packet networks

IEEE / Institute of Electrical and Electronics Engineers Incorporated

In certain scenarios, a Subsystem Reference block changes its position. It can happen during: 

1. Loading of top model which contains the Subsystem Reference block 
2. Synchronization of Subsystem Reference block's contents
3. Converting a subsystem to Subsystem Reference block 

This paper deals with an optimal control problem associated to the Kuramoto model describing the dynamical behavior of a network of coupled oscillators. Our aim is to design a suitable control function allowing us to steer the system to a synchronized configuration in which all the oscillators are aligned on the same phase. This control is computed via the minimization of a given cost functional associated with the dynamics considered. For this minimization, we propose a novel approach based on the combination of a standard Gradient Descent (GD) methodology with the recently-developed Random Batch Method (RBM) for the efficient numerical approximation of collective dynamics. Our simulations show that the employment of RBM improves the performances of the GD algorithm, reducing the computational complexity of the minimization process and allowing for a more efficient control calculation.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

The description generally relates to a system designed to synchronize the rendering of a media file between a master device and a sister device. The system is designed so that a media file is simultaneously rendered on a master device and a sister device beginning from identical temporal starting points.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

One aspect provides an optical communication system. The system includes an optical-to-digital converter, a frequency estimator and a symbol synchronizer. The optical-to-digital converter is configured to receive an optical OFDM bit stream including an OFDM symbol bearing payload data and a symbol header preceding the OFDM payload data. The frequency estimator is configured to determine a carrier frequency offset of the payload data from the symbol header. The symbol synchronizer is configured to determine a starting location of the payload data within the bit stream by cross-correlating a synchronization pattern within the symbol header with a model synchronization pattern stored by the symbol synchronizer.

Techniques are provided for increasing spectral efficiency over data channels in a storage or communication system. In some embodiments, data may be encoded and transmitted over multiple channels. The transmitted data from the multiple channels may be considered together as a channel bundle, thereby increasing the edge transitions of the group of signals to improve clock recovery and reduce coding constraints. In some embodiments, the channel bit size is reduced to maximize data rates based on the reduced coding constraints. Furthermore, the channel bundle has only one channel with timing markers, so that a receiver may receive information from the channel bundle and recover clocking based on the timing markers in the one channel.

A method includes receiving, at a multimedia device, a data stream representing multimedia content, the data stream comprising first timing information for the multimedia content, and metadata representing interactive event information associated with the multimedia content, the metadata comprising second timing information for the interactive event information. During the playback of the multimedia content, a first user interactive event is identified that is associated with a first time point in the playback of the multimedia content based on the interactive event information, and the first user interactive event is performed concurrent with the first time point in the playback of the multimedia content.

A method for play synchronization and a device using the same are provided. A first device stores time-based content play information. The first device plays content according to the time-based content play information. The first device transmits the time-based content play information to a second device so that the second device plays the content according to the time-based content play information. Accordingly, the content played by one device can be played by another device concurrently.

Methods, devices and system are provided. One method includes capturing activity data associated with activity of a user via a device. The activity data is captured over time, and the activity data is quantifiable by a plurality of metrics. The method includes storing the activity data in storage of the device and, from time to time, connecting the device with a computing device over a wireless communication link. The method defines using a first transfer rate for transferring activity data captured and stored over a period of time. The first transfer rate is used following startup of an activity tracking application on the computing device The method also defines using a second transfer rate for transferring activity data from the device to the computing device for display of the activity data in substantial-real time on the computing device.

In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

Systems and methods for discrete signal synchronization based on a known bit pattern are described. In one aspect of the present subject matter, a discrete signal synchronization system is configured to synchronize a preprocessed discrete signal with a modified discrete signal. The system comprises a processor and a synchronization module coupled to the processor. The synchronization module comprises an extraction module and comparison module. The extraction module determines a bit pattern from the modified discrete signal using Discrete Wavelet Transformation (DWT) and Singular Value Decomposition (SVD). The comparison module compares the determined bit pattern with a known bit pattern of the preprocessed discrete signal and records a time point at which the determined bit pattern matches with the known bit pattern of the preprocessed discrete signal as a synchronization point.

A method is provided for improving synchronization and information transmission in a communication system, including: generating a signal with a centrally symmetric part s(k) exploitable for synchronization; and sending the signal over a communication channel. The signal is based on a uniquely identifiable sequence c(l) from a set of sequences exploitable for information transmission. The centrally symmetric part s(k) is centrally symmetric in the shape of absolute value thereof. The centrally symmetric part s(k) is of arbitrary length N.

A system for a distributed repository includes an input interface and a processor. The input interface is to receive a request to change a portion of code. The processor is to determine a change reference and an existing reference, indicate to lock one or more repositories, determine whether swapping references is approved by a vote, and in the event that swapping references is approved by a vote, swap the references and indicate to unlock the one or more repositories.

Methods and apparatus for implementing time synchronization across exascale fabrics. A master clock node is coupled to a plurality of slave nodes via a fabric comprising a plurality of fabric switches and a plurality of fabric links, wherein each slave node is connected to the master clock node via a respective clock tree path that traverses at least one fabric switch. The fabric switches are configured to selectively forward master clock time data internally along paths with fixed latencies that bypass the switches' buffers and switch circuitry, which enables the entire clock tree paths to also have fixed latencies. The fixed latency of the clock tree path is determined for each slave node. The local clocks of the slave nodes are then synchronized with the master clock by using master clock time data received by each slave node and the fixed latency of the clock tree path from the master clock node to the slave node that is determined. Techniques for determining a clock rate mismatch between the master clock and a local clock is also provided.

A synchronization unit of a switchable gear changing transmission for a vehicle. The synchronization unit includes a friction ring having an outer installation surface and a synchronizer ring having an inner installation surface. The outer installation surface of the friction ring is shaped as a first geometrically structured profile. The inner installation surface of the synchronizer ring is shaped as a corresponding second geometrically structured profile. The first profile of the friction ring is configured to engage with the second profile of the synchronizer ring in such a manner that the friction ring is secured in the radial direction to the axis and in the circumferential direction at the synchronizer ring.

Cham : Springer, c2019.

Online Resource

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