IEEE / Institute of Electrical and Electronics Engineers Incorporated

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

The invention provides a variable tuning circuit capable of extending a variable range in a high frequency band, ensuring the value of L of an inductor to increase the value of Q of a circuit in a low frequency band, and preventing a reduction in gain, an increase in noise, and unstable oscillation. A variable tuning circuit includes: a first parallel resonance circuit that includes a varactor diode, a capacitor connected in series to the varactor diode, and a first inductor connected in parallel to the varactor diode and the capacitor; and a second parallel resonance circuit that includes a second inductor connected in parallel to the varactor diode with a direct current cut-off capacitor interposed therebetween. When the varactor diode has a maximum capacitance, a resonant frequency of the second parallel resonance circuit is set about a lowest frequency in a variable frequency range.

Provided is an oscillator including: a MEMS resonator for mechanically vibrating; an output oscillator circuit for oscillating at a resonance frequency of the MEMS resonator to output an oscillation signal; and a MEMS capacitor for changing a capacitance thereof caused by a change in a distance between an anode electrode and a cathode beam according to an environmental temperature.

A transmission line is provided in which a first portion of the transmission line is configured to be connected to a source, and a second portion of the transmission line is configured to be connected to a load. A capacitive element is coupled to the transmission line and is configured to compensate for an impedance difference between the load and at least one of the source or the transmission line, at a frequency within a frequency bandwidth of the load. A difference between an internal capacitance of the first portion of the transmission line and the second portion of the transmission line substantially matches the capacitance of the capacitive element.

An ice making device may include an ice tray, a water-supply part for supplying water to the ice tray, an electrostatic capacity sensor having two or more electrodes attached to the ice tray, a water quantity detecting section for detecting a water quantity in the ice tray on a basis of variation of an electrostatic capacity between the electrodes of the electrostatic capacity sensor, and an ice frozen detecting section for detecting water supplied to the ice tray having been frozen on the basis of the variation of the electrostatic capacity between the electrodes of the electrostatic capacity sensor. A control unit for the ice making device controls the water-supply part, an ice tray drive part and an ice detecting part on the basis of variation of the electrostatic capacity between the electrodes of the electrostatic capacity sensor.

In accordance with an embodiment, an adjustable capacitance circuit comprising a first branch comprising plurality of transistors having load paths coupled in series with a first capacitor. A method of operating the adjustable capacitance circuit includes programming a capacitance by selectively turning-on and turning-off ones of the plurality of transistors, wherein the load path of each transistor of the plurality of transistors is resistive when the transistor is on and is capacitive when the transistor is off.

A voltage of a first capacitor is compared with a threshold voltage and a signal corresponding to the comparison result is generated at each of a first timing during a period after the transfer of a positive charge has ended and before the transfer of a negative charge starts and a second timing during a period after the transfer of the negative charge has ended and before the transfer of the positive charge starts. In each of the case where a positive charge is transferred and the case where a negative charge is transferred, operations (digitization of an integrated value and a feedback operation) of a delta sigma modulator are performed.

A surge suppression device includes a micro electromechanical system (MEMS) switch electrically connected to a current path. Additionally, the surge suppression device includes a transient voltage suppression (TVS) device electrically connected in series to the MEMS switch. The surge suppression device is configured to protect electronic components from voltage surges or current surges.

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can